System and method for erasing a memory cell
View Patent ↗A method erases a memory cell of a semiconductor device that includes a group of memory cells. Each memory cell includes a group of storage regions. The method includes determining that each storage region of the group of storage regions of a first memory cell is to be erased and erasing the group of storage regions of the first memory cell via a single hot hole injection process.
1. A method for erasing a memory cell of a semiconductor device that includes a plurality of memory cells, each memory cell of the plurality of memory cells including a plurality of storage regions, the method comprising:
determining that each storage region of the plurality of storage regions of a first memory cell is to be erased; and
erasing the plurality of storage regions of the first memory cell via a single hot hole injection process, the erasing including:
applying a gate to substrate bias of about −4 volts to about −8 volts,
applying a source to substrate bias of about −1 volts to about 2 volts, and
applying a drain to substrate bias of about 5 volts to about 6 volts.
2. The method of claim 1 wherein the plurality of storage regions of the first memory cell includes two storage regions.
3. The method of claim 1 wherein the single hot hole injection process lowers a threshold voltage of the first memory cell to less than a predetermined value.
4. The method of claim 3 wherein the predetermined value is about 2 volts.
5. The method of claim 3 wherein the threshold voltage is lowered to less than the predetermined value within approximately 1 millisecond.
6. The method of claim 1 wherein the single hot hole injection process includes a band-to-band (BTB) hot hole injection process.
7. The method of claim 1 further comprising:
determining that a single storage region of the plurality of storage regions of a second memory cell is to be erased; and
erasing the single storage region of the second memory cell via a second single hot hole injection.
8. The method of claim 7 wherein the erasing the single storage region includes:
applying a gate to substrate bias of about −4 volts to about −8 volts,
applying a source to substrate bias of about −1 volts to about 2 volts, and
applying a drain to substrate bias of about 4 volts to about 5 volts.
9. The method of claim 7 wherein the second single hot hole injection lowers a threshold voltage of the single storage region in the second memory cell to less than a second predetermined value, a threshold voltage of at least one other storage region in the second memory cell not being lowered to less than the second predetermined voltage.
10. A method for erasing a memory cell of a semiconductor device, the memory cell including a gate region, a source region, and a drain region and including a plurality of storage regions, the method comprising:
applying a gate to substrate bias to the memory cell;
applying a source to substrate bias to the memory cell, the source to substrate bias ranging from approximately −1 volts to approximately 2 volts; and
applying a drain to substrate bias to the memory cell, the gate to substrate bias, the source to substrate bias, and the drain to substrate bias causing all of the plurality of storage regions of the memory cell to be erased.
11. The method of claim 10 wherein the gate to substrate bias ranges from approximately −4 volts to approximately −8 volts.
12. The method of claim 11 wherein the drain to substrate bias ranges from approximately 5 volts to approximately 6 volts.
13. The method of claim 10 wherein the applying the gate to substrate bias, the source to substrate bias, and the drain to substrate bias causes a threshold voltage of the plurality of storage regions of the memory cell to be lowered to less than a predetermined voltage.
14. The method of claim 13 wherein the predetermined voltage is 2 volts.
15. The method of claim 10 wherein the memory cell further includes a channel, a length of the channel ranging from about 100 Å to about 10,000 Å.
16. A memory cell comprising:
a substrate;
a first dielectric layer formed over the substrate;
a charge storage element configured to store two bits of data, the two bits of data being erased together by applying a gate to substrate bias of about −4 volts to about −8 volts, applying a source to substrate bias of about −1 volts to about 2 volts, and applying a drain to substrate bias of about 5 volts to about 6 volts;
an intergate dielectric formed over the charge storage element;
a control gate formed over the intergate dielectric;
a source region; and
a drain region, a distance from the source region to the drain region ranging from about 100 Å to about 10,000 Å.
17. The memory cell of claim 16 wherein the two bits of data are erased together via a single band-to-band induced hot hole injection.