Power interconnect structure for balanced bitline capacitance in a memory array
View Patent ↗According to one exemplary embodiment, a semiconductor die includes a memory core array situated over a substrate, where the memory core array includes a number of bitlines, where the bitlines can be situated in a first interconnect metal layer in the semiconductor die. The semiconductor die further includes an interconnect structure situated over the memory core array, where the interconnect structure is situated in a second interconnect metal layer in the semiconductor die and situated over each of the bitlines. The interconnect structure can include at least one interconnect line, which can form an angle with respect to the bitlines that can be greater than 0.0 degrees and less than or equal to 90.0 degrees. The interconnect structure can form one of a number of capacitances with each of the bitlines, where each of the capacitances can be substantially equal in value to each other of the capacitances.
1. A semiconductor die comprising:
a memory core array situated over a substrate, said memory core array comprising a plurality of bitlines, said plurality of bitlines being situated in a first interconnect metal layer in said semiconductor die;
an interconnect structure situated over said memory core array, said interconnect structure being situated in a second interconnect metal layer in said semiconductor die;
wherein said interconnect structure is situated over each of said plurality of bitlines, wherein said interconnect structure forms one of a plurality of capacitances with each of said plurality of bitlines, wherein each of said plurality of capacitances is substantially equal in value to each other of said plurality of capacitances, and wherein said at least one interconnect line forms an angle with respect to said plurality of bitlines, wherein said angle is greater than 0.0 degrees and less than or equal to 90.0 degrees.
2. A semiconductor die comprising:
a memory core array situated over a substrate, said memory core array comprising a plurality of bitlines, said plurality of bitlines being situated in a first interconnect metal layer in said semiconductor die;
an interconnect structure situated over said memory core array, said interconnect structure being situated in a second interconnect metal layer in said semiconductor die;
wherein said interconnect structure is situated over each of said plurality of bitlines, wherein said interconnect structure comprises at least one interconnect line, wherein said at least one interconnect line comprises a plurality of parallel interconnect lines, and wherein said each of said plurality of interconnect lines forms an angle with respect to said plurality of bitlines, wherein said angle is greater than 0.0 degrees and less than or equal to 90.0 degrees.
3. A semiconductor die comprising:
a memory core array situated over a substrate, said memory core array comprising a plurality of bitlines;
an interconnect structure situated over said memory core array, said interconnect structure being situated over each of said plurality of bitlines;
wherein said interconnect structure forms one of a plurality of capacitances with each of said plurality of bitlines, wherein each of said plurality of capacitances is substantially equal in value to each other of said plurality of capacitances, wherein said interconnect structure comprises first and second interconnect lines and an interconnect center portion, wherein said interconnect center portion is situated at an intersection of said first interconnect line and said second interconnect line.
4. The semiconductor die of claim 3 wherein said interconnect center portion is situated over a first area of one of said plurality of bitlines, said first interconnect line is situated over a second area of a second one of said plurality of bitlines, and said second interconnect line is situated over a third area of said second one of said plurality of bitlines.
5. The semiconductor die of claim 4 wherein said first area is substantially equal to a sum of said second area and said third area.
6. The semiconductor die of claim 3 wherein said first interconnect line forms an angle with respect to said plurality of bitlines, wherein said angle is between 0.0 degrees and 90.0 degrees.
7. The semiconductor die of claim 6 wherein said angle is approximately equal to 45.0 degrees.