Flexible latency in flash memory
View Patent ↗A method of reading data in and outputting data from a memory structure includes a buffer. In the present method, first read operation is undertaken to read a first set of data in the memory structure and provide data of the first set of data to the buffer, using an output clock. A first output operation is undertaken providing data read in the first read operation from the buffer, and a second read operation is undertaken to read a second set of data in the memory structure and provide data of the second set of data to the buffer, using the output clock. A second output operation is undertaken providing data read in the second read operation from the buffer. In the event that the completion of the first output operation would occur prior to the completion of the provision of the data of the second set of data to the buffer, a flexible time delay approach is undertaken so that, between the completion of the first output operation and the beginning of the second output operation, the minimum number of latencies are added as needed to insure that the provision of the data of the second set of data to the buffer is completed prior to the initiation of the second output operation.
1. A method of reading data in and outputting data from a memory structure comprising:
undertaking a first read operation to read a first set of data in the memory structure;
using an output clock, undertaking a first output operation to output data of the first set of data from the memory structure;
undertaking a second read operation to read a second set of data in the memory structure;
using the output clock, undertaking a second output operation to output data of the second set of data from the memory structure; and
in the event that the completion of the first output operation would occur prior to the completion of the second read operation, adding, between the completion of the first output operation and the beginning of the second output operation, the minimum number of output clock cycles needed to insure that the second read operation is completed prior to the initiation of the second output operation.
2. The method of claim 1 wherein the first output operation is initiated after completion of the first read operation.
3. The method of claim 1 wherein the second read operation is undertaken during the first output operation.
4. The method of claim 1 and further comprising a third read operation using an access line of the memory structure which is different from an access line of the memory structure used in the second read operation.
5. The method of claim 1 and further comprising a third read operation using an access line of the memory structure which is the same access line of the memory structure used in the second read operation.
6. The method of claim 1 wherein the memory structure comprises a buffer 54 , wherein through each read operation, data is provided to the buffer, and wherein through each output operation, data is provided from the buffer.
7. The method of claim 1 wherein the second read operation uses an access line of the memory structure different from an access line of the memory structure used in the first read operation.
8. The method of claim 1 wherein the second read operation uses an access line of the memory structure which is the same access line of the memory structure used in the first read operation.
9. A method of reading data in and outputting data from a memory structure including a buffer, comprising:
undertaking a first read operation to read a first set of data in the memory structure and provide data of the first set of data to the buffer;
using an output clock, undertaking a first output operation providing data read in the first read operation from the buffer;
undertaking a second read operation to read a second set of data in the memory structure and provide data of the second set of data to the buffer;
using the output clock, undertaking a second output operation providing data read in the second read operation from the buffer; and
in the event that the completion of the first output operation would occur prior to the completion of the provision of the data of the second set of data to the buffer, adding, between the completion of the first output operation and the beginning of the second output operation, the minimum number of output clock cycles needed to insure that the provision of the data of the second set of data to the buffer is completed prior to the initiation of the second output operation.
10. The method of claim 9 wherein the first output operation is initiated after completion of the first read operation.
11. The method of claim 10 wherein the second read operation is undertaken during the first output operation.
12. The method of claim 9 and further comprising a third read operation using an access line of the memory structure which is different from an access line of the memory structure used in the second read operation.
13. The method of claim 9 and further comprising a third read operation using an access line of the memory structure which is the same access line of the memory structure used in the second read operation.
14. The method of claim 9 wherein the second read operation uses an access line of the memory structure different from an access line of the memory structure used in the first read operation.
15. The method of claim 9 wherein the second read operation uses an access line of the memory structure which is the same access line of the memory structure used in the first read operation.