Method for achieving increased control over interconnect line thickness across a wafer and between wafers
View Patent ↗According to one exemplary embodiment, a method comprises a step of etching a trench in an ILD layer, said trench having sidewalls and a bottom surface. The method further comprises determining a height of the sidewalls of the trench. The method further comprises filling the trench with interconnect metal such the interconnect metal extends above the trench. According to this exemplary embodiment, the method further comprises performing a CMP process to remove a portion of the interconnect metal. In the present invention, the height of the sidewalls of the trench is utilized to control an amount of polishing performed in the CMP process. The remaining portion of interconnect metal in the trench forms an interconnect line, where the thickness of the interconnect line is controlled by utilizing the height of the sidewalls of the trench to control the amount of polishing in the CMP process.
1. A method comprising steps of:
etching a trench in an ILD layer, said trench having sidewalls and a bottom surface;
determining a height of said sidewalls of said trench;
filling said trench with interconnect metal such that said interconnect metal extends above said trench;
performing a CMP process to remove a portion of said interconnect metal;
wherein said height of said sidewalls of said trench is used to adjust said CMP process to control an amount of polishing performed in said CMP process.
2. The method of claim 1 further comprising a step of depositing a barrier layer on said sidewalls and said bottom surface of said trench and on said ILD stack after said step of determining said height of said sidewalls of said trench and prior to said step of filling said trench with said interconnect metal.
3. The method of claim 2 wherein said step of filling said trench with said interconnect metal comprises depositing said interconnect metal on said barrier layer.
4. The method of claim 1 wherein said interconnect metal comprises copper.
5. The method of claim 1 wherein a remaining portion of said interconnect metal in said trench forms an interconnect line.
6. The method of claim 5 wherein a thickness of said interconnect line is controlled by utilizing said height of said sidewalls of said trench to control said amount of polishing in said CMP process.
7. The method of claim 1 wherein said ILD layer comprises a top dielectric layer and a bottom dielectric layer, said top dielectric layer comprising TEOS oxide.
8. The method of claim 7 wherein said bottom dielectric layer comprises silicon nitride.
9. A method comprising steps of:
etching a trench in an ILD layer, said trench having sidewalls and a bottom surface;
determining a height of said sidewalls of said trench;
depositing a barrier layer on said sidewalls and said bottom surface of said trench and on said ILD layer;
depositing interconnect metal on said barrier layer such that said interconnect metal fills said trench;
performing a CMP process to remove a portion of said interconnect metal;
wherein said height of said sidewalls of said trench is used to adjust said CMP process to control an amount of polishing performed in said CMP process.
10. The method of claim 9 wherein said interconnect metal comprises copper.
11. The method of claim 9 wherein a remaining portion of said interconnect metal in said trench forms an interconnect line.
12. The method of claim 11 wherein a thickness of said interconnect line is controlled by utilizing said height of said sidewalls of said trench to control said amount of polishing performed in said CMP process.
13. The method of claim 9 wherein said ILD layer comprises a top dielectric layer and a bottom dielectric layer, said top dielectric layer comprising TEOS oxide.
14. The method of claim 13 wherein said bottom dielectric layer comprises silicon nitride.
15. The method of claim 9 wherein said step of performing said CMP process comprises removing a portion of said barrier layer situated on said ILD layer.
16. A method comprising steps of:
etching a trench in an ILD layer, said trench having sidewalls and a bottom surface;
determining a height of said sidewalls of said trench;
depositing a barrier layer on said sidewalls and said bottom surface of said trench and on said ILD layer;
depositing interconnect metal on said barrier layer such that said interconnect metal fills said trench;
performing a CMP process to remove a portion of said interconnect metal such that a remaining portion of said interconnect metal forms an interconnect line;
wherein said height of said sidewalls of said trench is used to adjust said CMP process to control an amount of polishing performed in said CMP process and to control a thickness of said interconnect line.
17. The method of claim 16 wherein said interconnect metal comprises copper.
18. The method of claim 16 wherein said step of performing said CMP process comprises removing a portion of said barrier layer situated on said ILD layer.
19. The method of claim 16 wherein said ILD layer comprises a top dielectric layer and a bottom dielectric layer, said top dielectric layer comprising TEOS oxide.
20. The method of claim 19 wherein said bottom dielectric layer comprises silicon nitride.