Semiconductor component and method of manufacture
View Patent ↗A semiconductor component having a memory cell coupled to a trench line and a method for manufacturing the semiconductor component. Trenches having sidewalls are formed in a semiconductor substrate and a trench line is formed in each trench. A polysilicon insert is formed between the trench line and each sidewall of the trench. A column of memory cells is formed between the trenches where each memory cell of the column of memory cells has a gate structure, a source region, and a drain region. The source regions of the column of memory cells are electrically coupled to the trench line on one side of the column of memory cells via one of the polysilicon inserts. The drain regions of the column of memory cells are electrically coupled to the trench line adjacent the opposite side of the column of memory cells via another of the polysilicon inserts.
1. A semiconductor component, comprising:
a substrate having a major surface;
a trench having first and second sidewalls extending from the major surface into the substrate;
a first column of memory cells adjacent the first sidewall; and
a trench line disposed in the trench, wherein the trench line is electrically coupled to the first column of memory cells.
2. The semiconductor component of claim 1 , wherein the first column of memory cells comprises at least one memory cell having a gate structure, a drain region, and a source region.
3. The semiconductor component of claim 2 , further including a first connector, wherein the first connector electrically couples one of the source region or the drain region to the trench line.
4. The semiconductor component of claim 3 , further including a second connector, wherein the second connector electrically couples the other of the source region or the drain region to the trench line.
5. The semiconductor component of claim 3 , wherein the trench line serves as a bit line.
6. The semiconductor component of claim 2 , further including a drain connector, wherein the drain connector electrically couples the drain region of the at least one memory cell to the trench line.
7. The semiconductor component of claim 6 , further including a source connector, wherein the source connector electrically couples the source region of the at least one memory cell to the trench line.
8. The semiconductor component of claim 2 , further including a source connector, wherein the source connector electrically couples the source region of the at least one memory cell to the trench line.
9. The semiconductor component of claim 8 , further including a second column of memory cells, wherein the second column of memory cells is adjacent the second sidewall and comprises at least one memory cell having a gate structure, a drain region, and a source region.
10. The semiconductor component of claim 8 , further including another drain connector, wherein the another drain connector electrically couples the drain region of the at least one memory cell of the second column of memory cells to the trench line.
11. The semiconductor component of claim 8 , further including another source connector, wherein the another source connector electrically couples the drain region of the at least one memory cell of the second column of memory cells to the trench line.
12. The semiconductor component of claim 1 , further including a second column of memory cells, wherein the second column of memory cells is adjacent the second sidewall and comprises at least one memory cell having a gate structure, a drain region, and a source region.
13. A memory device, comprising:
a first memory cell having a gate structure, a drain region, and a source region, the gate structure disposed on a semiconductor substrate;
a second memory cell having a gate structure, a drain region, and a source region, the gate structure of the second memory cell disposed on the semiconductor substrate and wherein the source region of the second memory cell is coupled to the source region of the first memory cell, and wherein the first and second memory cells cooperate to form a first column of memory cells;
a first trench adjacent the first column of memory cells the first trench extending into the substrate; and
a first trench line disposed in the first trench, wherein the source regions of the first and second memory cells are coupled to the first trench line.
14. The memory device of claim 13 , further including a second trench adjacent the first column of memory cells, the second trench extending into the substrate and a second trench line disposed in the second trench, wherein the drain regions of the first and second memory cells are coupled to the second trench line.
15. The memory device of claim 14 , further including:
a third memory cell having a gate structure disposed on the semiconductor substrate, a drain region, and a source region; and
a fourth memory cell having a gate structure disposed on the semiconductor substrate, a drain region, and a source region, wherein the source region of the fourth memory cell is coupled to the source region of the third memory cell and the source regions of the third and fourth memory cells are coupled to the second trench line, and wherein the third and fourth memory cells cooperate to form a second column of memory cells.
16. The memory device of claim 15 , wherein the second trench line is between the first and second columns of memory cells.
17. The memory device of claim 15 , further including a third trench adjacent the second column of memory cells the third trench extending into the substrate and a third trench line disposed in the third trench.
18. The memory device of claim 17 , wherein the drain regions of the third and fourth memory cells are coupled to the third trench line.
19. The memory device of claim 18 , wherein the first trench line serves as a first bit line, the second trench line serves as a second bit line, and the third trench line serves as a third bit line.
20. The memory device of claim 15 , further including a first bit line coupled to the drain regions of the first and second memory cells.
21. The memory device of claim 20 , further including a second bit line coupled to the drain regions of the second and third memory cells.
22. The memory device of claim 13 , further including a first bit line coupled to the drain regions of the first and second memory cells.