Memory device having silicided bitlines and method of forming the same
View Patent ↗A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate, a bottom dielectric, a charge storing layer, and a top dielectric in a stacked gate configuration. Silicided buried bitlines, which function as a source and a drain, are formed within the substrate. The silicided bitlines have a reduced resistance, which greatly reduces the number of bitline contacts necessary in an array of memory devices.
1. A method of fabricating a memory device comprising:
providing a semiconductor substrate;
forming a stacked gate over the semiconductor substrate, the stacked gate including a bottom dielectric layer, a charge storing dielectric layer formed over the bottom dielectric layer, a top dielectric layer formed over the charge storing dielectric layer, and a gate electrode formed over the top dielectric layer;
forming a pair of silicided buried bitlines within the substrate, the silicided buried bitlines functioning as a source and a drain for the memory device;
forming a wordline pad over the stacked gate, the step of forming a wordline pad comprising:
forming a word line conductor along a first direction perpendicular to the direction along which the silicided buried bitlines extend; and
selectively etching portions of the wordline conductor substantial above each silicided buried bitline; and
forming at least one local interconnect in electrical contact with the wordline pad, said interconnect electrically connecting the wordline pad to at least one adjacent wordline pad.
2. The method according to claim 1 , wherein the step of forming the silicided buried bitlines comprises:
implanting N-type ion species into the semiconductor substrate laterally adjacent the stacked gate;
forming a pair of spacers adjacent lateral sidewalls of the stacked gate;
depositing a metal over the implanted semiconductor substrate;
reacting the deposited metal with the semiconductor substrate.
3. The method according to claim 2 , wherein the spacers function as a self-aligned mask for formation of the silicided buried bitlines.
4. A method of forming a non-volatile memory unit having a plurality of memory devices organized in rows and columns, where a plurality of bitlines are oriented substantially parallel to one another along a first direction, the method comprising:
providing a semiconductor substrate:
forming a plurality of stacked gates over the semiconductor substrate, the stacked gates each including a bottom dielectric layer, a charge storing dielectric layer formed over the bottom dielectric layer, a top dielectric layer formed over the charge storing dielectric layer, and a gate electrode formed over the top dielectric layer;
forming pairs of silicided buried bitlines within the substrate, the silicided buried bitlines functioning as a source and a drain for each memory device; and
forming a single bitline contact per 100 or more rows of memory devices, the a single bitline contact being in physical and electrical connection with at least one of the silicided buried bitlines.
5. The method according to claim 4 , comprising forming a single bitline contact per at least 200 memory devices.