Differentially mis-aligned contacts in flash arrays to calibrate failure modes
View Patent ↗A method and apparatus for calibrating failures in semiconductor memory devices due to contact mask misalignment includes: providing a plurality of semiconductor memory devices on a die; providing a contact mask with a plurality of known offsets; creating a plurality of contacts on the die using the contact mask; determining which devices on the die fail; and creating a pass/fail map for the devices. The pass/fail map can be used to determine the range of allowed misalignment and the amount of misalignment, providing a better understanding of how contact mask misalignment affects the yield and reliability of the memory devices. The pass/fail map may also be used for comparison with a pass/fail map created after the arrays have been subjected to a known stress.
1. A method for calibrating failures in semiconductor memory devices due to contact mask misalignment, comprising the steps of:
(a) providing a first plurality of semiconductor memory devices on a first die;
(b) providing a contact mask with a plurality of known offsets;
(c) creating a first plurality of contacts on the first die using the contact mask;
(d) determining which of the first plurality of semiconductor memory devices on the first die fail; and
(e) creating a first pass/fail map for the first plurality of semiconductor memory devices.
2. The method of claim 1 , wherein the determining step (d) comprises:
(d1) measuring a parameter for each of the first plurality of semiconductor memory devices on the first die.
3. The method of claim 2 , wherein the parameter comprises one or more of the group consisting of:
charge leakage;
charge loss; and
bit failure.
4. The method of claim 1 , further comprising:
(f) determining a range of contact mask misalignment allowed for passing semiconductor memory devices on the first die using the first pass/fail map.
5. A method for calibrating failures in semiconductor memory devices due to contact mask misalignment, comprising the steps of:
(a) providing a plurality of semiconductor memory devices on a die;
(b) providing a contact mask with a plurality of known offsets;
(c) creating a plurality of contacts on the die using the contact mask;
(d) determining which of the plurality of semiconductor memory devices on the die fail;
(e) creating a first pass/fail map for the plurality of semiconductor memory devices; and
(f) determining a range of contact mask misalignment allowed for passing semiconductor memory devices using the first pass/fail map.
6. A method for calibrating failures in semiconductor memory devices due to contact mask misalignment, comprising the steps of:
(a) providing a plurality of semiconductor memory devices on a die;
(b) providing a contact mask with a plurality of known offsets;
(c) creating a plurality of contacts on the die using the contact mask;
(d) determining which of the plurality of semiconductor memory devices on the die fail;
(e) creating a first pass/fail map for the plurality of semiconductor memory devices;
(f) subjecting the plurality of semiconductor memory devices on the die to a known stress;
(g) creating a second pass/fail map for the devices after subjecting the plurality of semiconductor memory devices to the known stress; and
(h) comparing the second pass/fail map with the first pass/fail map.
7. A method for calibrating failures in semiconductor memory devices due to contact mask misalignment, comprising the steps of:
(a) providing a first plurality of semiconductor memory devices on a first die;
(b) providing a contact mask with a plurality of known offsets;
(c) creating a first plurality of contacts on the first die using the contact mask;
(d) determining which of the first plurality of semiconductor memory devices on the first die fail;
(e) creating a first pass/fail map for the first plurality of semiconductor memory devices;
(f) creating a second plurality of contacts on a second die using the contact mask;
(g) determining which of a second plurality of semiconductor memory devices on the second die fail;
(h) creating a second pass/fail map for the second plurality of semiconductor memory devices on the second die; and
(i) comparing the second pass/fail map with the first pass/fail map to determine an amount of misalignment of the contact mask.