Method of programming dual cell memory device to store multiple data states per cell
View Patent ↗A method of programming a multi-level, dual cell memory device. The method includes independently programming a first charge storing cell and a second charge storing cell to respective data states, the data states selected from a blank program level or one of a plurality of charged program levels. Also disclosed is a method of reading the multi-level, dual cell memory device using a plurality of reference currents.
1. A method of programming and subsequently reading a charge trapping dielectric memory device having a first charge storing cell adjacent a first conductive region and a second charge storing cell adjacent a second conductive region, comprising:
programming the memory device, including:
programming the first charge storing cell to store a first amount of charge, the first amount of charge corresponding to a first cell data state selected from a blank program level or one of a plurality of charged program levels; and
programming the second charge storing cell to store a second amount of charge, the second amount of charge corresponding to a second cell data state selected from the blank program level or one of the plurality of charged program levels; and reading one of the charge storing cells, including:
comparing a first conductive region to second conductive region current against a plurality of reference currents to determine the data state to which the read charge storing cell is programmed, and
wherein the reference currents include a first reference current derived from a maximum complimentary bit disturb threshold voltage condition of a first associated dynamic reference and a minimum lowest program level threshold voltage condition of a second associated dynamic reference.
2. The method according to claim 1 , wherein each data state for one of the charge storing cells establishes a distinguishable threshold voltage for the memory device.
3. The method according to claim 1 , wherein channel hot electron injection is used to program the charge storing cells to the charged program levels.
4. The method according to claim 1 , wherein during programming of the first charge storing cell to one of the charged program levels, a bias potential is applied to the second conductive region.
5. The method according to claim 1 , wherein during programming of the second charge storing cell to one of the charged program levels, a bias potential is applied to the first conductive region.
6. The method according to claim 1 , wherein the plurality of charged program levels include a lowest program level, a middle program level and a highest program level.
7. The method according to claim 1 , wherein deriving the first reference current includes averaging the maximum complimentary bit disturb threshold voltage condition and the minimum lowest program level threshold voltage condition.
8. The method according to claim 1 , further comprising outputting a value corresponding to the blank program level if the first conductive region to second conductive region current is less than the first reference current.
9. The method according to claim 1 , wherein the reference currents include a second reference current derived from the minimum lowest program level threshold voltage condition of the second associated dynamic reference and a minimum middle program level threshold voltage condition of the third associated dynamic reference and a third reference current derived from the minimum middle program level threshold voltage condition of the third associated dynamic reference and a minimum highest program level threshold voltage condition of a fourth associated dynamic reference.
10. The method according to claim 9 , wherein deriving the second reference current includes averaging the minimum lowest program level threshold voltage condition and the minimum middle program level threshold voltage condition and deriving the third reference current includes averaging the minimum middle program level threshold voltage condition and the minimum highest program level threshold voltage condition.
11. The method according to claim 9 , wherein the first and fourth dynamic references are implemented by reading a single dynamic reference in opposite directions.
12. The method according to claim 1 , wherein the reading is conducted by a reverse read operation wherein a voltage is applied to the conductive region adjacent the unread charge storing cell.
13. A method of programming and subsequently reading a charge trapping dielectric memory device having a first charge storing cell adjacent a first conductive region and a second charge storing cell adjacent a second conductive region, comprising:
programming the memory device, including:
programming the first charge storing cell to store a first amount of charge, the first amount of charge corresponding to a first cell data state selected from a blank program level or one of a plurality of charged program levels; and
programming the second charge storing cell to store a second amount of charge, the second amount of charge corresponding to a second cell data state selected from the blank program level or one of the plurality of charged program levels; and
reading one of the charge storing cells, including:
comparing a first conductive region to second conductive region current against a plurality of reference currents to determine the data state to which the read charge storing cell is programmed, and
outputting a first digital word value associated with the determined data state for the read charge storing cell, the first digital word being at least two bits in length.
14. The method according to claim 13 , further comprising reading the other of the charge storing cells and outputting a second digital word value associated with the data state for the other of the charge storing cell, the second digital word being at least two bits in length.
15. A method of reading a charge trapping dielectric memory device having a first charge storing cell adjacent a first conductive region and a second charge storing cell adjacent a second conductive region, and wherein each charge storing cell is independently programmed to a program level selected from a blank program level or one of a plurality of charged program levels, comprising:
generating a plurality of reference currents including a first reference current derived from a maximum complimentary bit disturb threshold voltage condition of a first dynamic reference associated with the memory device and a minimum lowest program level threshold voltage condition of a second dynamic reference associated with the memory device; and
comparing a current through a channel interposed between the first and second conductive regions against the plurality of reference currents to determine the program level to which a read one of the charge storing cells is programmed.
16. The method according to claim 15 , wherein the charge storing cells are located in a continuous dielectric charge storing layer and the channel is control by a single gate electrode.
17. The method according to claim 15 , further comprising outputting a data value corresponding to the program level of the read charge storing cells.
18. The method according to claim 17 , wherein the data value is a digital word of at least two bits.
19. The method according to claim 15 , wherein deriving the first reference current includes averaging the maximum complimentary bit disturb threshold voltage condition and the minimum lowest program level threshold voltage condition.
20. The method according to claim 15 , further comprising outputting a value corresponding to the blank program level if the current through the channel is less than the first reference current.