Patent Assignment
Reel/Frame 019069/0360
Assignment of Assignor's Interest
Recorded: 2007-03-27
Received: 2007-03-27
Pages: 6
Assignor
SPANSION INC.
Executed: 2007-01-31
Assignee
SPANSION LLC
915 DEGUIGNE DRIVE, P.O. BOX 3453, MAIL STOP 250, SUNNYVALE, CA, 94088-3453, UNITED STATES
Covered Properties
(36)
Semiconductor Device with Core and Periphery Regions
Application:
10/869,774 →
Uv-Blocking Etch Stop Layer for Reducing Uv-Induced Charging of Charge Storage Layer in Memory Devices in Beol Processing
Application:
10/861,437 →
Narrow Wide Spacer
Application:
10/821,312 →
Uv-Blocking Layer for Reducing Uv-Induced Charging of Sonos Dual-Bit Flash Memory Devices in Beol Processing
Application:
10/818,112 →
Bitline Hard Mask Spacer Flow for Memory Cell Scaling
Application:
10/770,673 →
Flash Memory Cell with Uv Protective Layer
Application:
10/770,260 →
Tightly Spaced Gate Formation Through Damascene Process
Application:
10/716,209 →
Dual Cell Memory Device Having a Top Dielectric Stack
Application:
10/716,230 →
Memory Cell Array with Staggered Local Inter-Connect Structure
Application:
10/685,044 →
Recess Channel Flash Architecture for Reduced Short Channel Effect
Application:
10/683,649 →
Memory Device and Method Using Positive Gate Stress to Recover Overerased Cell
Application:
10/677,790 →
A Flash Memory Cell with Drain and Source Formed by Diffusion of a Dopant from a Silicide
Application:
10/661,720 →
Method of Fabricating a Floating Gate
Application:
10/655,936 →
Partially De-Coupled Core and Periphery Gate Module Process
Application:
10/619,797 →
Method of Fabricating a Planar Structure Charge Trapping Memory Cell Array with Rectangular Gates and Reduced Bit Line Resistance
Application:
10/463,643 →
Memory Device Having a Thin Top Dielectric and Method of Erasing Same
Application:
10/459,102 →
Memory Device with Reduced Operating Voltage Having Dielectric Stack
Application:
10/430,604 →
Method of Programming and Reading a Dual Cell Memory Device
Application:
10/422,276 →
Method of Dual Cell Memory Device Operation for Improved End-of-Life Read Margin
Application:
10/422,092 →
Method of Controlling Program Threshold Voltage Distribution of a Dual Cell Memory Device
Application:
10/422,090 →
Method of Programming a Dual Cell Memory Device
Application:
10/422,489 →
Method of Programming Dual Cell Memory Device to Store Multiple Data States Per Cell
Application:
10/413,800 →
Memory Device Having Improved Periphery and Core Isolation
Application:
10/407,999 →
Method of Forming Core and Periphery Gates Including Two Critical Masking Steps to Form a Hard Mask in a Core Region That Includes a Critical Dimension Less Than Achievable at a Resolution Limit of Lithography
Application:
10/382,744 →
Protection of Charge Trapping Dielectric Flash Memory Devices from Uv-Induced Charging in Beol Processing
Application:
10/368,696 →
Uv-Blocking Layer for Reducing Uv-Induced Charging of Sonos Dual-Bit Flash Memory Devices in Beol Processing
Application:
10/358,589 →
Method of Improving Dynamic Reference Tracking for Flash Memory Unit
Application:
10/357,879 →
Method for Reading a Non-Volatile Memory Cell Adjacent to an Inactive Region of a Non-Volatile Memory Cell Array
Application:
10/353,558 →
Structure and Method for Reducing Standing Waves in a Photoresist
Application:
10/350,472 →
Method for Improving Read Margin in a Flash Memory Device
Application:
10/349,293 →
Dielectric Memory Cell Structure with Counter Doped Channel Region
Application:
10/342,549 →
Flash Memory Device Having Four-Bit Cells
Application:
10/315,632 →
System for Programming a Non-Volatile Memory Cell
Application:
10/307,667 →
Pre-Charge Method for Reading a Non-Volatile Memory Cell
Application:
10/307,749 →
Program Algorithm Including Soft Erase for Sonos Memory Device
Application:
10/305,756 →
Organic Spin-on Anti-Reflective Coating Over Inorganic Anti-Reflective Coating
Application:
10/262,221 →