Granted Patent B1

US 6,919,247 · App. 10/655,936 · Granted Jul 19, 2005

Abstract

Claims (23)

1. A method of fabricating a floating gate for a semiconductor device, said method comprising:

depositing an undoped polycrystalline silicon layer on a tunnel oxide layer, wherein said undoped polycrystalline silicon layer has a first thickness;

depositing a doped polycrystalline silicon layer on said undoped polycrystalline silicon layer, wherein said doped polycrystalline silicon layer has a second thickness, and wherein said undoped polycrystalline silicon layer and said doped polycrystalline silicon layer form said floating gate having a third thickness, wherein said doped polycrystalline silicon layer includes dopant material throughout said second thickness; and

performing a plurality of thermal processes such that said floating gate comprises a plurality of grains, each grain being smaller than the grains of a floating gate formed using only doped polycrystalline silicon.

2. The method as recited in claim 1 wherein said doped polycrystalline silicon layer includes an N-type dopant material.

3. The method as recited in claim 2 wherein N-type dopant material is phosphorous.

4. The method as recited in claim 1 wherein said third thickness is approximately a sum of said first thickness and said second thickness.

5. The method as recited in claim 1 wherein said first thickness is approximately one third of said third thickness, and wherein said second thickness is approximately two thirds of said third thickness.

6. The method as recited in claim 1 wherein said first thickness is approximately fifty percent of said third thickness, and wherein said second thickness is approximately fifty percent of said third thickness.

7. The method as recited in claim 1 wherein said semiconductor device is a flash memory device.

8. A method of fabricating a stacked gate structure for a semiconductor device, said method comprising:

forming a tunnel oxide layer on a surface of a semiconductor substrate;

depositing an undoped polycrystalline silicon layer on said tunnel oxide layer, wherein said undoped polycrystalline silicon layer has a first thickness;

depositing a doped polycrystalline silicon layer on said undoped polycrystalline silicon layer, wherein said doped polycrystalline silicon layer has a second thickness, and wherein said undoped polycrystalline silicon layer and said doped polycrystalline silicon layer form a floating gate having a third thickness, wherein said doped polycrystalline silicon layer includes dopant material throughout said second thickness;

performing a plurality of thermal processes such that said floating gate comprises a plurality of grains, each grain being smaller than the grains of a floating gate formed using only doped polycrystalline silicon;

forming a ONO (Oxide-Nitride-Oxide) layer on said floating gate; and

forming a control gate on said ONO layer.

9. The method as recited in claim 8 wherein said doped polycrystalline silicon layer includes an N-type dopant material.

10. The method as recited in claim 9 wherein N-type dopant material is phosphorous.

11. The method as recited in claim 8 wherein said third thickness is approximately a sum of said first thickness and said second thickness.

12. The method as recited in claim 8 wherein said first thickness is approximately one third of said third thickness, and wherein said second thickness is approximately two thirds of said third thickness.

13. The method as recited in claim 8 wherein said first thickness is approximately fifty percent of said third thickness, and wherein said second thickness is approximately fifty percent of said third thickness.

14. The method as recited in claim 8 wherein said semiconductor device is a flash memory device.

Assignments (11)