Granted Patent B1

US 6,927,129 · App. 10/821,312 · Granted Aug 9, 2005

Abstract

Claims (38)

1. A method of manufacturing a semiconductor device comprising:

a) depositing a first layer over a periphery transistor comprising a gate stack, a drain side sidewall and a source side sidewall and over a core transistor comprising a gate stack, a source side sidewall and a drain side sidewall;

b) etching said first layer wherein a portion of said first layer remains on said source side sidewall and on said drain side sidewall of said periphery transistor and on said source side sidewall and on said drain side sidewall of said core transistor;

c) etching said first layer from said source side sidewall of said core transistor while preserving said first layer on said drain side sidewall of said core transistor;

d) depositing a second layer over said periphery transistor and said core transistor; and

e) etching said second layer wherein a portion of said second layer remains on said first layer formed on said source side sidewall and on said drain side sidewall of said periphery transistor and wherein said second layer remains on said source side sidewall and on said drain side sidewall of said core transistor.

2. The method as described in claim 1 wherein said first layer is silicon nitride.

3. The method as described in claim 1 wherein said first layer is silicon oxide and silicon nitride.

4. The method as described in claim 1 wherein said second layer is silicon nitride.

5. The method as described in claim 1 wherein said b) is a chemical etch, wherein said chemical etch does not remove material from said gate stack of said periphery transistor and does not remove material from said gate stack of said core transistor.

6. The method as described in claim 1 wherein said c) is a self aligned source etch.

7. The method as described in claim 1 wherein said first layer is thicker than said second layer.

8. The method as described in claim 1 wherein said core transistor is a flash memory cell.

9. A method for simultaneously manufacturing a wide sidewall spacer on a periphery transistor and a narrow sidewall spacer on a core transistor comprising:

a) depositing a first layer over a periphery transistor comprising a gate stack, a drain side sidewall and a source side sidewall and over a core transistor comprising a gate stack, a source side sidewall and a drain side sidewall;

b) etching said first layer wherein a portion of said first layer remains on said source side sidewall and on said drain side sidewall of said periphery transistor and on said source side sidewall and said drain side sidewall of said core transistor;

c) masking and etching said first layer from said source side sidewall while preserving said first layer on said drain sidewall of said core transistor;

d) depositing a second layer over said periphery transistor and said core transistor; and

e) etching said second layer wherein a portion of said second layer remains on said first layer formed on said source side sidewall and said drain side sidewall of said periphery transistor resulting in a wide sidewall spacer and wherein said second layer remains on said source side sidewall and said drain side sidewall of said core transistor resulting in a narrow sidewall spacer.

10. The method as described in claim 9 wherein said first layer is silicon nitride.

11. The method as described in claim 9 wherein said first layer is silicon oxide and silicon nitride.

12. The method as described in claim 9 wherein said second layer is silicon nitride.

13. The method as described in claim 9 wherein said b) is a chemical etch, wherein said chemical etch does not remove material from said gate stack of said periphery transistor and does not remove material from said gate stack of said core transistor.

14. The method as described in claim 9 wherein said first layer is thicker than said second layer.

15. The method as described in claim 9 wherein said core transistor is a flash memory cell.

16. A method for simultaneously manufacturing a semiconductor comprising a wide sidewall spacer and a narrow sidewall spacer comprising:

a) depositing a first layer over a first transistor comprising a gate stack, a drain side sidewall and a source side sidewall and over a second transistor comprising a gate stack, a source side sidewall and a drain side sidewall;

b) etching said first layer wherein a portion of said first layer remains on said source side sidewall and on said drain side sidewall of said first transistor and on said source side sidewall and on said drain side sidewall of said second transistor;

c) etching said first layer from said source side sidewall of said second transistor while preserving said first layer on said drain sidewall of said second transistor;

d) depositing a second layer over said first transistor and said second transistor; and

e) etching said second layer wherein a portion of said second layer remains on said first layer formed on said source side sidewall and on said drain side sidewall of said first transistor and wherein said second layer remains on said source side sidewall and on said drain side sidewall of said second transistor.

17. The method as described in claim 16 wherein said first transistor is a periphery transistor.

18. The method as described in claim 16 wherein said second transistor is a core transistor.

19. The method as described in claim 18 wherein said core transistor is a flash memory cell.

20. The method as described in claim 16 wherein said first layer comprises silicon oxide and silicon nitride.

21. The method as described in claim 16 wherein said second layer comprises nitride.

22. The method as described in claim 16 wherein said c) is a self aligned source etch.

23. The method as described in claim 16 wherein said first layer is thicker than said second layer.

Assignments (11)