Memory device having a thin top dielectric and method of erasing same
View Patent ↗A non-volatile memory device includes a semiconductor substrate and a source and drain within the substrate. A dielectric stack is formed over the substrate. The dielectric stack includes a thin top dielectric layer. A gate electrode is formed over the dielectric stack. The memory device is operative to perform a direct tunneling channel erase operation in which a pair of charge storing cells within a charge storing layer are erased via direct tunneling through the thin top dielectric layer.
1. A memory device comprising:
a semiconductor substrate;
a source and a drain formed from buried bitlines disposed within the semiconductor substrate, said source and drain defining a body region therebetween;
a bottom dielectric layer formed over the semiconductor substrate, said bottom dielectric layer having a thickness;
a charge storing layer formed over the bottom dielectric layer, said charge storing layer having a conductivity such that at least a first charge can be stored in a first charge storing cell adjacent the drain and at least a second charge can be stored in a second charge storing cell adjacent the source;
a top dielectric layer formed over the charge storing layer, said top dielectric having a thickness less than the thickness of the bottom dielectric layer; and
a gate electrode formed over the top dielectric layer.
2. The memory device according to claim 1 , wherein the top dielectric layer is effective to increase the probability that, during an erase operation, electrons within the charge storing layer will directly tunnel through the top dielectric layer to exit the charge storing layer into the gate electrode.
3. The memory device according to claim 2 , wherein the bottom dielectric layer is effective to decrease the probability that electrons will overcome a potential barrier of the bottom dielectric layer and escape from the charge storing layer into the substrate.
4. The memory device according to claim 1 , wherein the top dielectric layer has a thickness of about 25 angstroms (Å) to less than about 50 angstroms (Å).
5. A memory device comprising:
a semiconductor substrate;
a source and a drain formed from buried bitlines disposed within the semiconductor substrate, said source and drain defining a body region therebetween;
a bottom dielectric layer formed over the semiconductor substrate, said bottom dielectric layer having a thickness;
a charge storing layer formed over the bottom dielectric layer, said charge storing charge storing cell adjacent the drain and at least a second charge cane stored in a second charge storing cell adjacent the source;
a top dielectric layer formed over the charge storing layer, said top dielectric having a thickness of about 25 angstroms (Å) to about 50 angstroms (Å) which is less than the thickness of the bottom dielectric layer; and
a gate electrode formed over the top dielectric layer.
6. The memory device according to claim 5 , wherein the bottom dielectric layer has a thickness of about 50 angstroms (Å) to about 80 angstroms (Å).
7. The memory device according to claim 5 , wherein the charge storing layer has a thickness of about 50 angstroms (Å) to about 80 angstroms (Å).
8. The memory device according to claim 5 , wherein the bottom dielectric layer, the top dielectric layer and the charge storing layer form a dielectric stack having a thickness of about 130 angstroms (Å) to about 190 angstroms (Å).
9. A method of performing an erase operation on a non-volatile memory device having a source and a drain within a substrate, a bottom dielectric layer formed over a top surface of the substrate, a charge storing dielectric layer formed over the bottom dielectric layer, a top dielectric layer formed over the charge storing dielectric layer, and a gate electrode formed over the top dielectric layer, the memory device having been programmed by storing charge in a portion of the charge storing layer adjacent the drain, the method comprising the simultaneous steps of:
applying a positive erase voltage of about +4 Volts to about +5 Volts to the gate electrode; and
connecting at least one of the drain or the source to a potential of about −4 Volts to about −5 Volts.
10. The method according to claim 9 , wherein the charge storing dielectric layer includes two bits, both bits being erased simultaneously.
11. The method according to claim 9 , further comprising:
applying a potential of about +4 Volts to about +5 Volts to the gate electrode; connecting the drain to a potential of about −4 Volts to about −5 Volts; and grounding the source.
12. The method according to claim 9 , wherein the simultaneous steps occur for a duration of at least about 1 ms.
13. A method of simultaneously erasing at least two charge storing cells on a non-volatile memory device having a pair of bitlines within a substrate, a charge trapping dielectric stack on a top surface of the substrate, said charge trapping dielectric stack including a bottom dielectric layer, a charge storing dielectric layer end a top dielectric layer, said charge storing cells being disposed within the charge storing layer of the charge trapping dielectric stack, and a gate layer on the charge storing dielectric stack, said method comprising:
decreasing the thickness of the top dielectric layer of the dielectric stack, said decreased thickness being effective to increase the probability that, during an erase operation, electrons within the charge storing cells of the charge storing layer will directly tunnel through the top dielectric layer to exit the charge storing cells;
applying a positive gate erase voltage of less than about +10 Volts to the gate layer;
one of (i) applying a zero potential to a first bitline and a second bitline, or (ii) applying a potential of about −4 Volts to about −5 Volts to the first bitline and the second bitline.
14. The method according to claim 13 , further comprising:
setting a potential barrier height of the bottom dielectric layer of the charge trapping dielectric stack such that the potential barrier height is effective to decrease the probability that, during an erase operation, electrons within the charge storing layer will overcome a potential barrier of the bottom dielectric layer and tunnel through the bottom dielectric layer.
15. The method according to claim 14 , further comprising:
reducing a thickness of the bottom dielectric layer, while maintaining the retention properties of the cell.
16. The method according to claim 13 , further including:
facilitating direct tunneling from the charge storing dielectric layer into the gate layer by decreasing the thickness of the top dielectric layer to between about 25 angstroms (Å) and about 50 angstroms (Å).