IP Library › Assignment 043062/0183
Patent Assignment
Reel/Frame 043062/0183

RELEASE OF SECURITY INTEREST

Recorded: 2017-06-29 Received: 2017-06-29 Pages: 11
Assignor
Assignee
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT, SAN JOSE, CA, 95134-1709, UNITED STATES
Covered Applications (64)
CHARGE CONTROL THAT KEEPS CONSTANT INPUT VOLTAGE SUPPLIED TO BATTERY PACK
App. No. 10/954,754
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SYSTEM AND METHOD FOR MULTI-BIT FLASH READS USING DUAL DYNAMIC REFERENCES
App. No. 10/933,588
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SEMICONDUCTOR INTEGRATED CIRCUIT FOR DRIVING LIQUID CRYSTAL PANEL
App. No. 10/930,856
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SIGNAL DETECTION APPARATUS, SIGNAL DETECTION METHOD, SIGNAL TRANSMISSION SYSTEM, AND COMPUTER READABLE PROGRAM TO EXECUTE SIGNAL TRANSMISSION
App. No. 10/896,967
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CUS FORMATION BY ANODIC SULFIDE PASSIVATION OF COPPER SURFACE
App. No. 10/885,944
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MEMORY DEVICE AND METHODS OF USING NEGATIVE GATE STRESS TO CORRECT OVER-ERASED MEMORY CELLS
App. No. 10/863,673
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CHARGE/DISCHARGE CONTROL CIRCUIT AND SECONDARY BATTERY
App. No. 10/854,781
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NARROW BITLINE USING SAFIER FOR MIRRORBIT
App. No. 10/755,430
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DUAL CELL MEMORY DEVICE HAVING A TOP DIELECTRIC STACK
App. No. 10/716,230
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FREQUENCY MEASUREMENT CIRCUIT
App. No. 10/700,454
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TEST STRUCTURE FOR DETERMINING ELECTROMIGRATION AND INTERLAYER DIELECTRIC FAILURE
App. No. 10/636,162
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STRUCTURE AND METHOD FOR PREVENTING UV RADIATION DAMAGE IN A MEMORY CELL AND IMPROVING CONTACT CD CONTROL
App. No. 10/460,278
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MEMORY DEVICE HAVING A THIN TOP DIELECTRIC AND METHOD OF ERASING SAME
App. No. 10/459,102
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PLL SEMICONDUCTOR DEVICE WITH TESTABILITY, AND METHOD AND APPARATUS FOR TESTING SAME
App. No. 10/452,149
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PLL CIRCUIT INCLUDING A VOLTAGE OSCILLATOR AND A METHOD FOR CONTROLLING A VOLTAGE CONTROLLED OSCILLATOR
App. No. 10/443,105
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THRESHOLD VOLTAGE ADJUSTMENT METHOD OF NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
App. No. 10/369,496
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DC-DC CONVERTER, DUTY-RATIO SETTING CIRCUIT AND ELECTRIC APPLIANCE USING THEM
App. No. 10/345,352
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TREATMENT OF DIELECTRIC MATERIAL TO ENHANCE ETCH RATE
App. No. 10/331,938
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METHOD FOR AND STRUCTURE FORMED FROM FABRICATING A RELATIVELY DEEP ISOLATION STRUCTURE
App. No. 10/324,989
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MASTER/SLAVE METHOD FOR A ZQ-CIRCUITRY IN MULTIPLE DIE DEVICES
App. No. 10/306,364
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MEMORY CIRCUIT FOR SUPPRESSING BIT LINE CURRENT LEAKAGE
App. No. 10/306,080
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FURNACE SYSTEM AND METHOD FOR SELECTIVELY OXIDIZING A SIDEWALL SURFACE OF A GATE CONDUCTOR BY OXIDIZING A SILICON SIDEWALL IN LIEU OF A REFRACTORY METAL SIDEWALL
App. No. 10/290,841
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MRAM DATA LINE CONFIGURATION AND METHOD OF OPERATION
App. No. 10/281,601
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RECEIVING CIRCUIT
App. No. 10/278,902
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GROUND STRUCTURE FOR PAGE READ AND PAGE WRITE FOR FLASH MEMORY
App. No. 10/264,387
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BELLOWS ZOOM MICROSCOPE
App. No. 10/256,746
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HOT-PLUGGABLE OVER-VOLTAGE TOLERANT INPUT/OUTPUT CIRCUIT
App. No. 10/256,680
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METHODS FOR FABRICATING AND PLANARIZING DUAL POLY SCALABLE SONOS FLASH MEMORY
App. No. 10/244,369
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PROCESS TO IMPROVE THE VSS LINE FORMATION FOR HIGH DENSITY FLASH MEMORY AND RELATED STRUCTURE ASSOCIATED THEREWITH
App. No. 10/179,723
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HIGHER PROGRAM VT AND FASTER PROGRAMMING RATES BASED ON IMPROVED ERASE METHODS
App. No. 10/173,262
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SYSTEM AND METHOD FOR MULTI-BIT FLASH READS USING DUAL DYNAMIC REFERENCES
App. No. 10/136,173
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PROGRAMMABLE ON-CHIP TERMINATION DEVICE
App. No. 10/136,111
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DC/DC CONVERTER CONTROL CIRCUIT AND DC/DC CONVERTER SYSTEM WITH POWER SAVING MODE IN ACCORDANCE WITH AN EXTERNAL CONTROL SIGNAL
App. No. 10/134,751
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Method for multi-bit flash reads using dual dynamic references
App. No. 60/372,361
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ARCHITECTURE FOR PROGRAMMABLE ON-CHIP TERMINATION
App. No. 10/102,256
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FREQUENCY MEASUREMENT CIRCUIT
App. No. 10/088,605
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USE OF HIGH-K DIELECTRIC MATERIAL IN MODIFIED ONO STRUCTURE FOR SEMICONDUCTOR DEVICES
App. No. 10/097,912
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SYSTEM FOR SETTING MEMORY VOLTAGE THRESHOLD
App. No. 10/096,338
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DYNAMIC SWAPPING OF MEMORY BANK BASE ADDRESSES
App. No. 10/061,914
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OVERVOLTAGE-PROTECTIVE DEVICE FOR POWER SYSTEM, AC/DC CONVERTER AND DC/DC CONVERTER CONSTITUTING THE POWER SYSTEM
App. No. 10/041,594
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Treatment of dielectric material to enhance etch rate
App. No. 60/344,191
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PLANAR TRANSISTOR STRUCTURE USING ISOLATION IMPLANTS FOR IMPROVED VSS RESISTANCE AND FOR PROCESS SIMPLIFICATION
App. No. 10/032,646
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MONOS DEVICE HAVING BURIED METAL SILICIDE BIT LINE
App. No. 10/022,798
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MASTER/SLAVE METHOD FOR A ZQ-CIRCUITRY IN MULTIPLE DIE DEVICES
App. No. 10/022,880
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SYSTEM AND METHOD FOR RESTORING THE MARK AND SPACE RATIO OF A CLOCKING SIGNAL OUTPUT FROM AN OSCILLATOR
App. No. 10/013,869
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STORING OF GLOBAL PARAMETER DEFAULTS AND USING THEM OVER TWO OR MORE DESIGN PROJECTS
App. No. 09/989,761
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DIFFERENTIAL SIGNAL OUTPUT APPARATUS, SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS HAVING THE DIFFERENTIAL SIGNAL OUTPUT APPARATUS, AND DIFFERENTIAL SIGNAL TRANSMISSION SYSTEM
App. No. 09/973,767
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METHOD FOR APPLYING INSTRUCTIONS TO MICROPROCESSOR IN TEST MODE
App. No. 09/972,319
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METHOD AND APPARATUS FOR MASK AND/OR COUNTER ADDRESS REGISTERS READBACK ON THE ADRESS BUS IN SYNCHRONOUS SINGLE AND MULTI-PORT MEMORIES
App. No. 09/966,838
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CIRCUIT AND METHOD FOR TESTING PHYSICAL LAYER FUNCTIONS OF A COMMUNICATION NETWORK
App. No. 09/935,283
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OPERATIONAL AMPLIFIER WITH EXTENDED OUTPUT VOLTAGE RANGE
App. No. 09/916,925
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USING HOT CARRIER INJECTION TO CONTROL OVER-PROGRAMMING IN A NON-VOLATILE MEMORY CELL HAVING AN OXIDE-NITRIDE-OXIDE (ONO) STRUCTURE
App. No. 09/902,332
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HIGH DENSITY FLASH EEPROM ARRAY WITH SOURCE SIDE INJECTION
App. No. 09/892,685
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NOVEL POWER ON RESET CIRCUIT FOR A MICROCONTROLLER
App. No. 09/887,955
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NOVEL METHOD AND SYSTEM FOR INTERACTION BETWEEN A PROCESSOR AND A POWER ON RESET CIRCUIT TO DYNAMICALLY CONTROL POWER STATES IN A MICROCONTROLLER
App. No. 09/887,923
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METHOD OF PROGRAMMING A NON-VOLATILE MEMORY CELL USING A DRAIN BIAS
App. No. 09/880,367
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DOT-INVERSION DATA DRIVER FOR LIQUID CRYSTAL DISPLAY DEVICE
App. No. 09/824,345
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WAFER CARRIER, WAFER CARRIER COMPONENTS, AND CMP SYSTEM FOR POLISHING A SEMICONDUCTOR TOPOGRAPHY
App. No. 09/823,446
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CHARGE/DISCHARGE CONTROL CIRCUIT AND SECONDARY BATTERY
App. No. 09/816,108
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HYBRID PRODUCT TERM AND LOOK-UP TABLE-BASED PROGRAMMABLE LOGIC DEVICE WITH IMPROVED SPEED AND AREA EFFICIENCY
App. No. 09/805,518
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HIGHER PROGRAM VT AND FASTER PROGRAMMING RATES BASED ON IMPROVED ERASE METHODS
App. No. 09/796,282
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TAILORED ERASE METHOD USING HIGHER PROGRAM VT AND HIGHER NEGATIVE GATE ERASE
App. No. 09/795,854
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PARASITIC CAPACITANCE CANCELING CIRCUIT
App. No. 09/772,718
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PLL SEMICONDUCTOR DEVICE WITH TESTABILITY, AND METHOD AND APPARATUS FOR TESTING SAME
App. No. 09/757,492
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