Semiconductor integrated circuit for driving liquid crystal panel
Lower level of data latch holding a digital image data and a positive selector arranged immediately above positive gradation voltage line, for selecting positive analog gradation voltage of positive gradation levels are take as a set, and upper level of data latch holding a digital image data and a negative selector arranged immediately above negative gradation voltage line, for selecting negative analog gradation voltage of negative gradation levels are take as a set. Two sets are arranged in alignment in vertical direction. A plurality of sets of vertically aligned sets are arranged horizontally to shorten a length in horizontal direction with respect to gradation voltage lines.
1. A gradation wiring for a display comprising:
wiring for respective gradation levels of a first gradation level range for outputting voltage of said first gradation level range when total number of gradation levels of the display is divided into a plurality of fractions;
wiring for respective gradation level of a second gradation level range different from said first gradation level range, for outputting voltage of said second gradation level range and being arranged alternately with the wiring of respective gradation level of said first gradation level range.
2. A gradation wiring for a display as set forth in claim 1 , wherein said second gradation level range is the gradation level range having gradation level in sequence with the gradation level in said first gradation level range.
3. A gradation wiring for a display as set forth in claim 2 , wherein the wiring of respective gradation level of said first gradation level range is the wiring of a front half portion of the gradation level range when total number of gradation levels of said display is divided into two, and the wiring of respective gradation level of said second gradation level range is the wiring of a rear half portion of the gradation level range when total number of gradation levels of said display is divided into two.
4. A gradation wiring for a display as set forth in claim 1 , wherein the wiring of respective gradation levels of said first and second gradation level ranges are wiring for outputting the gradation voltage to a liquid crystal display.
5. A gradation wiring for a display as set forth in claim 1 , which further comprises:
a first ladder resistor connected with the wiring of respective gradation levels of said first gradation level range; and
a second ladder resistor connected with the wiring of respective gradation levels of said second gradation level range.
6. A gradation wiring for a display as set forth in claim 5 , which further comprises:
a first reference voltage input terminal connected for making voltage of the wiring of respective gradation levels of said first gradation level range at the same potential; and
a second reference voltage input terminal connected for making voltage of the wiring of respective gradation levels of said second gradation level range at the same potential.
7. A gradation wiring for a display as set forth in claim 6 , wherein a flow direction of the current flowing through said first ladder resistor and a flow direction of the current flowing through said second ladder resistor are the same when a voltage is applied between said first and second reference voltage input terminals.
8. A gradation wiring for a display as set forth in claim 6 , wherein a flow direction of the current flowing through said first ladder resistor and a flow direction of the current flowing through said second ladder resistor are mutually opposite direction when a voltage is applied between said first and second reference voltage input terminals.
9. A gradation wiring for a display as set forth in claim 1 , which further comprises:
a minimum gradation level reference voltage input terminal connected to a wiring indicative of a minimum gradation level among said wiring;
a maximum gradation level reference voltage input terminal connected to a wiring indicative of a maximum gradation level among said wiring;
two predetermined gradation levels reference voltage input terminals connected to wiring indicative of the same predetermined gradation level.
10. A gradation wiring for a display as set forth in claim 3 , which further comprises:
a minimum gradation level reference voltage input terminal connected to a wiring indicative of a minimum gradation level among said wiring;
a maximum gradation level reference voltage input terminal connected to a wiring indicative of a maximum gradation level among said wiring;
two predetermined gradation levels reference voltage input terminals connected to wiring indicative of the same predetermined gradation level.
11. A gradation wiring for a display as set forth in claim 9 , which further comprises a switching element for connecting and disconnecting said two predetermined gradation level reference voltage input terminals.
12. A gradation wiring for a display as set forth in claim 11 , wherein said switching element is an element of combination of N-channel and P-channel transfer gates.
13. A gradation wiring for a display as set forth in claim 11 , wherein said switching element includes only N-channel transfer gate.
14. A gradation wiring for a display as set forth in claim 11 , wherein said switching element includes only P-channel transfer gate.
15. A gradation wiring for a display as set forth in claim 1 , wherein the wiring of respective gradation level of said first gradation level range and the wiring of respective gradation level of said second gradation level range are arranged in the same layer.
16. A gradation wiring for a display as set forth in claim 1 , wherein the wiring of respective gradation level of said first gradation level range and the wiring of respective gradation level of said second gradation level range are arranged in different layers.
17. A driver for a liquid crystal display comprising:
wiring for respective gradation levels of a first gradation level range for outputting voltage of said first gradation level range when total number of gradation levels of the display is divided into a plurality of fractions;
wiring for respective gradation level of a second gradation level range different from said first gradation level range, for outputting analog gradation voltage of respective gradation levels of said second gradation level range and being arranged alternately with the wiring of respective gradation level of said first gradation level range;
a first ladder resistor connected between wiring of respective gradation levels of said first gradation level range;
a second ladder resistor connected between wiring of respective gradation levels of said second gradation level range;
a first reference voltage input terminal connected for making voltages of the wiring of said first gradation level range at the same potential;
a second reference voltage input terminal connected for making voltages of the wiring of said second gradation level range at the same potential; and
a decoder for converting input digital gradation value into an analog gradation value on the basis of the analog gradation voltage value output from the wiring of respective gradation levels of said first and second gradation level ranges.
18. A stress test method for a driver of a liquid crystal display having wiring for respective gradation levels of a first gradation level range for outputting voltage of said first gradation level range when total number of gradation levels of the display is divided into a plurality of fractions, and wiring for respective gradation level of a second gradation level range different from said first gradation level range, for outputting voltage of said second gradation level range and being arranged alternately with the wiring of respective gradation level of said first gradation level range, comprising the steps of:
applying a first potential to wiring of a predetermined gradation level of said first gradation level range, applying a second potential to wiring of a predetermined gradation level of said second gradation level range, and whereby applying a stress voltage higher than the reference input voltage between said wiring; and
applying said reference input voltages of respective gradation levels to the wiring of predetermined gradation levels of said first and second gradation level ranges and inspecting presence or absence of abnormality of output voltage by measuring voltages output from the wiring of overall gradation levels.