Patent Assignment
Reel/Frame 036036/0001
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2015-06-30
Received: 2015-06-30
Pages: 153
Assignor
SPANSION, LLC
Executed: 2015-06-01
Assignee
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT, SAN JOSE, CA, 95134, UNITED STATES
Covered Applications
(92)
STYRENE ACRYLATE HYBRID TONER PROCESS UTILIZING A LOW VOC (VOLATILE ORGANIC COMPOUND) COALESCENT AGENT IN TONER SHELLS
App. No. 14/794,756
→
Method and Apparatus for Fast Frequency Acquisition in PLL System
App. No. 14/794,770
→
LOW-SPURIOUS FRACTIONAL N-FREQUENCY DIVIDER AND METHOD OF USE
App. No. 14/794,782
→
TONER COMPOSITIONS WITH OPTIMIZED BETA-CARBOXYETHYL ACRYLATE SHELL LATEX FOR IMPROVED PARTICLE FORMATION AND MORPHOLOGY
App. No. 14/794,746
→
Method and Device for Processing Motion Events
App. No. 14/736,162
→
OPERATING SYSTEM VIRTUALIZATION FOR HOST CHANNEL ADAPTERS
App. No. 13/948,146
→
SIGMA-DELTA MODULATOR FOR PLL CIRCUITS
App. No. 11/363,049
→
NON-VOLATILE MEMORY AND METHOD OF CONTROLLING THE SAME
App. No. 11/342,947
→
CLOCK GENERATION CIRCUIT AND CLOCK GENERATION METHOD
App. No. 11/312,392
→
REDUNDANCY SUBSTITUTION METHOD, SEMICONDUCTOR MEMORY DEVICE AND INFORMATION PROCESSING APPARATUS
App. No. 11/311,485
→
SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING THE SAME
App. No. 11/261,743
→
VARIABLE CAPACITY CIRCUIT AND CONTROL METHOD OF VARIABLE CAPACITY CIRCUIT
App. No. 11/216,000
→
EXPOSURE SYSTEM, SEMICONDUCTOR DEVICE, AND METHOD FOR FABRICATING THE SEMICONDUCTOR DEVICE
App. No. 11/215,246
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NON-VOLATILE MEMORY DEVICE AND ERASING METHOD THEREFOR
App. No. 11/215,889
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MEMORY SYSTEM AND TEST METHOD THEREFOR
App. No. 11/173,735
→
METHOD OF PROGRAMMING A RESISTIVE MEMORY DEVICE
App. No. 11/166,572
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RESISTIVE MEMORY DEVICE WITH IMPROVED DATA RETENTION
App. No. 11/165,005
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SELF-ALIGNED STI SONOS
App. No. 11/113,509
→
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE THAT ERASES STORED DATA AFTER A PREDETERMINED TIME PERIOD WITHOUT THE USE OF A TIMER CIRCUIT
App. No. 11/087,735
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VARIABLE DENSITY AND VARIABLE PERSISTENT ORGANIC MEMORY DEVICES, METHODS, AND FABRICATION
App. No. 11/034,071
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PHOTOSENSITIVE POLYMERIC MEMORY ELEMENTS
App. No. 10/951,370
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VOLTAGE CONTROLLED OSCILLATOR AND PLL CIRCUIT
App. No. 10/939,513
→
SYSTEMS AND METHODS FOR ADJUSTING PROGRAMMING THRESHOLDS OF POLYMER MEMORY CELLS
App. No. 10/919,846
→
SIGNAL DETECTION APPARATUS, SIGNAL DETECTION METHOD, SIGNAL TRANSMISSION SYSTEM, AND COMPUTER READABLE PROGRAM TO EXECUTE SIGNAL TRANSMISSION
App. No. 10/896,967
→
CUS FORMATION BY ANODIC SULFIDE PASSIVATION OF COPPER SURFACE
App. No. 10/885,944
→
CASCODE AMPLIFIER CIRCUIT FOR GENERATING AND MAINTAINING A FAST, STABLE AND ACCURATE BIT LINE VOLTAGE
App. No. 10/844,116
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FLASH MEMORY DEVICE
App. No. 10/838,215
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MEMORY DEVICE AND METHODS OF USING AND MAKING THE DEVICE
App. No. 10/818,261
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TESTING FOR OPERATING LIFE OF A MEMORY DEVICE WITH ADDRESS CYCLING USING A GRAY CODE SEQUENCE
App. No. 10/791,417
→
STRUCTURE FOR INCREASING DRIVE CURRENT IN A MEMORY ARRAY AND RELATED METHOD
App. No. 10/759,809
→
NARROW BITLINE USING SAFIER FOR MIRRORBIT
App. No. 10/755,430
→
FLASH MEMORY WITH BURIED BIT LINES
App. No. 10/738,322
→
NEUTRON DETECTING DEVICE
App. No. 10/728,510
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METHOD AND STRUCTURE FOR PROTECTING NROM DEVICES FROM INDUCED CHARGE DAMAGE DURING DEVICE FABRICATION
App. No. 10/701,780
→
CURRENT PULSE RECEIVING CIRCUIT
App. No. 10/681,306
→
SELF ASSEMBLY OF CONDUCTING POLYMER FOR FORMATION OF POLYMER MEMORY CELL
App. No. 10/677,042
→
METHOD OF MANUFACTURING A SEMICONDUCTOR MEMORY WITH DEUTERATED MATERIALS
App. No. 10/672,093
→
CONTROL METHOD OF NON-VOLATILE SEMICONDUCTOR MEMORY CELL AND NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
App. No. 10/665,205
→
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
App. No. 10/662,810
→
SEMICONDUCTOR MEMORY ENABLING CORRECT SUBSTITUTION OF REDUNDANT CELL ARRAY
App. No. 10/658,428
→
HIGH DENSITY FLOATING GATE FLASH MEMORY AND FABRICATION PROCESSES THEREFOR
App. No. 10/660,420
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MEMORY CIRCUIT WITH REDUNDANT CONFIGURATION
App. No. 10/652,035
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FULLY ISOLATED DIELECTRIC MEMORY CELL STRUCTURE FOR A DUAL BIT NITRIDE STORAGE DEVICE AND PROCESS FOR MAKING SAME
App. No. 10/631,199
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ANALOG SWITCH CIRCUIT
App. No. 10/625,738
→
SILICON CONTAINING MATERIAL FOR PATTERNING POLYMERIC MEMORY ELEMENT
App. No. 10/614,484
→
METHOD OF FABRICATING A PLANAR STRUCTURE CHARGE TRAPPING MEMORY CELL ARRAY WITH RECTANGULAR GATES AND REDUCED BIT LINE RESISTANCE
App. No. 10/463,643
→
STRUCTURE AND METHOD FOR PREVENTING UV RADIATION DAMAGE IN A MEMORY CELL AND IMPROVING CONTACT CD CONTROL
App. No. 10/460,278
→
MEMORY DEVICE HAVING A THIN TOP DIELECTRIC AND METHOD OF ERASING SAME
App. No. 10/459,102
→
PLL SEMICONDUCTOR DEVICE WITH TESTABILITY, AND METHOD AND APPARATUS FOR TESTING SAME
App. No. 10/452,149
→
PLL CIRCUIT INCLUDING A VOLTAGE OSCILLATOR AND A METHOD FOR CONTROLLING A VOLTAGE CONTROLLED OSCILLATOR
App. No. 10/443,105
→
MEMORY DEVICE WITH REDUCED OPERATING VOLTAGE HAVING DIELECTRIC STACK
App. No. 10/430,604
→
METHOD AND SYSTEM FOR IMPROVING SHORT CHANNEL EFFECT ON A FLOATING GATE DEVICE
App. No. 10/431,322
→
STRUCTURE AND METHOD FOR A TWO-BIT MEMORY CELL
App. No. 10/429,140
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FREQUENCY SYNTHESIZER CIRCUIT
App. No. 10/419,206
→
PHOTOSENSITIVE POLYMERIC MEMORY ELEMENTS
App. No. 10/405,272
→
APPARATUS AND METHOD FOR A SENSE AMPLIFIER CIRCUIT THAT SAMPLES AND HOLDS A REFERENCE VOLTAGE
App. No. 10/389,149
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FAST BANDGAP REFERENCE CIRCUIT FOR USE IN A LOW POWER SUPPLY A/D BOOSTER
App. No. 10/379,744
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IMPLANT DAMAGE REMOVAL BY LASER THERMAL ANNEALING
App. No. 10/378,885
→
SEMICONDUCTOR DEVICE INCLUDING A VOLTAGE MONITORING CIRCUIT
App. No. 10/373,739
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THRESHOLD VOLTAGE ADJUSTMENT METHOD OF NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
App. No. 10/369,496
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COMPENSATED OSCILLATOR CIRCUIT FOR CHARGE PUMPS
App. No. 10/358,498
→
FLASH MEMORY CELL PROGRAMMING METHOD AND SYSTEM
App. No. 10/342,585
→
FLASH MEMORY DEVICES WITH OXYNITRIDE DIELECTRIC AS THE CHARGE STORAGE MEDIA
App. No. 10/342,032
→
MEMORY DEVICE HAVING A P+ GATE AND THIN BOTTOM OXIDE AND METHOD OF ERASING SAME
App. No. 10/341,881
→
METHOD AND SYSTEM FOR TESTING TUNNEL OXIDE ON A MEMORY-RELATED STRUCTURE
App. No. 10/339,536
→
METHOD OF ALTERNATING GROUNDED/FLOATING POLY LINES TO MONITOR SHORTS
App. No. 10/288,871
→
CONTROL OF MEMORY ARRAYS UTILIZING ZENER DIODE-LIKE DEVICES
App. No. 10/287,363
→
STACKED ORGANIC MEMORY DEVICES AND METHODS OF OPERATING AND FABRICATING
App. No. 10/287,612
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MEMORY DEVICE HAVING RESISTIVE ELEMENT COUPLED TO REFERENCE CELL FOR IMPROVED RELIABILITY
App. No. 10/285,909
→
SYSTEM AND METHOD OF FORMING A PASSIVE LAYER BY A CMP PROCESS
App. No. 10/284,769
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NITROGEN OXIDATION TO REDUCE ENCROACHMENT
App. No. 10/284,866
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RECEIVING CIRCUIT
App. No. 10/278,902
→
GROUND STRUCTURE FOR PAGE READ AND PAGE WRITE FOR FLASH MEMORY
App. No. 10/264,387
→
METHOD FOR REDUCING DRAIN INDUCED BARRIER LOWERING IN A MEMORY DEVICE
App. No. 10/265,001
→
ORGANIC SPIN-ON ANTI-REFLECTIVE COATING OVER INORGANIC ANTI-REFLECTIVE COATING
App. No. 10/262,221
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FLASH MEMORY HAVING IMPROVED CORE FIELD ISOLATION IN SELECT GATE REGIONS
App. No. 10/260,061
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FLOATING GATE MEMORY DEVICE WITH HOMOGENEOUS OXYNITRIDE TUNNELING DIELECTRIC
App. No. 10/232,487
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METHOD OF FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE BY DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING AN OVERDRIVE CURRENT MEASUREMENT TECHNIQUE AND A DEVICE THEREBY FABRICATED
App. No. 10/225,052
→
METHOD AND SYSTEM FOR DETECTING TUNNEL OXIDE ENCROACHMENT ON A MEMORY DEVICE
App. No. 10/217,965
→
SYSTEM AND METHOD FOR ERASE VOLTAGE CONTROL DURING MULTIPLE SECTOR ERASE OF A FLASH MEMORY DEVICE
App. No. 10/210,378
→
SEMICONDUCTOR MEMORY AND METHOD OF DRIVING THE SAME
App. No. 10/207,056
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TEST STRUCTURE FOR MEASURING EFFECT OF TRENCH ISOLATION ON OXIDE IN A MEMORY DEVICE
App. No. 10/190,420
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DC/DC CONVERTER CONTROL CIRCUIT AND DC/DC CONVERTER SYSTEM WITH POWER SAVING MODE IN ACCORDANCE WITH AN EXTERNAL CONTROL SIGNAL
App. No. 10/134,751
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METHOD OF DETECTING AND DISTINGUISHING STACK GATE EDGE DEFECTS AT THE SOURCE OR DRAIN JUNCTION
App. No. 10/126,193
→
METHOD FOR REDUCING SHALLOW TRENCH ISOLATION EDGE THINNING ON THIN GATE OXIDES TO IMPROVE PERIPHERAL TRANSISTOR RELIABILITY AND PERFORMANCE FOR HIGH PERFORMANCE FLASH MEMORY DEVICES
App. No. 10/126,814
→
PARTIAL PAGE PROGRAMMING OF MULTI LEVEL FLASH
App. No. 10/074,495
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TWO-STEP SOURCE SIDE IMPLANT FOR IMPROVING SOURCE RESISTANCE AND SHORT CHANNEL EFFECT IN DEEP SUB-0.18MUM FLASH MEMORY TECHNOLOGY
App. No. 10/053,256
→
OXIDIZING PRETREATMENT OF ONO LAYER FOR FLASH MEMORY
App. No. 10/010,280
→
N-GATE/N-SUBSTRATE OR P-GATE/P-SUBSTRATE CAPACITOR TO CHARACTERIZE POLYSILICON GATE DEPLETION EVALUATION
App. No. 09/917,440
→
LOAD/STORE MICROPACKET HANDLING SYSTEM
App. No. 09/915,109
→
CLOCKED BASED METHOD AND DEVICES FOR MEASURING VOLTAGE-VARIABLE CAPACITANCES AND OTHER ON-CHIP PARAMETERS
App. No. 09/825,027
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INTERFACE APPARATUS
App. No. 09/766,001
→