Self-aligned STI SONOS
View Patent ↗Methods 300 and 350 are disclosed for fabricating shallow isolation trenches and structures in multi-bit SONOS flash memory devices. One method aspect 300 comprises forming 310 a multi-layer dielectric-charge trapping-dielectric stack 420 over a substrate 408 of the wafer 402 , for example, an ONO stack 420 , removing 312 the multi-layer dielectric-charge trapping-dielectric stack 420 in a periphery region 406 of the wafer 402 , thereby defining a multi-layer dielectric-charge trapping-dielectric stack 420 in a core region 404 of the wafer 402 . The method 300 further comprises forming 314 a gate dielectric layer 426 over the periphery region 406 of the substrate 408 , forming 316 a first polysilicon layer 428 over the multi-layer dielectric-charge trapping-dielectric stack 420 in the core region 402 and the gate dielectric 426 in the periphery region 406 , then concurrently forming 318 an isolation trench 438 in the substrate 408 in the core region 404 and in the periphery region 406 . Thereafter, the isolation trenches are filled 326 with a dielectric material 446 , and a second polysilicon layer 452 that is formed 332 over the first polysilicon layer 428 and the filled trenches 438 , forming an self-aligned STI structure 446 . The method 300 avoids ONO residual stringers at STI edges in the periphery region, reduces active region losses, reduces thinning of the periphery gate oxide and the ONO at the STI edge, and reduces dopant diffusion during isolation implantations due to reduced thermal process steps.
1. A method of fabricating shallow isolation trench structures in a wafer, comprising:
forming a multi-layer dielectric-charge trapping-dielectric stack over a substrate of the wafer;
removing the multi-layer dielectric-charge trapping-dielectric stack in a periphery region of the wafer, thereby defining a multi-layer dielectric-charge trapping-dielectric stack in a core region of the wafer;
forming a gate dielectric layer over the periphery region of the substrate;
forming a first polysilicon layer over the multi-layer dielectric-charge trapping-dielectric stack in the core region and the gate dielectric in the periphery region;
concurrently forming an isolation trench in the substrate, through the first polysilicon layer and the multi-layer dielectric-charge trapping-dielectric stack in the core region and through the first polysilicon layer and the gate dielectric layer in the periphery region, thereby defining isolation trenches;
filling the isolation trenches with a dielectric material; and
forming a second polysilicon layer over the first polysilicon layer and the filled trenches.
2. The method of claim 1 , further comprising implanting a dopant ion species into the substrate associated with the isolation trenches after concurrently forming the isolation trenches in the core region and in the periphery region, and before filling the isolation trenches with a dielectric material.
3. The method of claim 2 , wherein the dopant ion species implanted into the substrate associated with the isolation trenches is one of a B, a BF 2 , and a p-type dopant ion species.
4. The method of claim 1 , further comprising planarizing the wafer to separate individual isolation structures after filling the isolation trenches with a dielectric material and before forming a second polysilicon layer over the first polysilicon layer and the filled trenches.
5. The method of claim 4 , wherein the planarizing the wafer to separate individual isolation structures is accomplished using a chemical mechanical polishing process.
6. The method of claim 1 , wherein the forming a multi-layer dielectric-charge trapping-dielectric stack over the substrate of the wafer comprises forming a first oxide layer overlying the substrate of the wafer, a nitride layer overlying the first oxide layer, and a second oxide layer overlying the nitride layer.
7. The method of claim 1 , wherein the shallow isolation trenches are fabricated in a multi-bit SONOS flash memory.
8. A method of fabricating shallow isolation trench structures in a wafer, comprising:
forming a multi-layer dielectric-charge trapping-dielectric stack over a substrate of the wafer;
removing the multi-layer dielectric-charge trapping-dielectric stack in a periphery region of the wafer, thereby defining a multi-layer dielectric-charge trapping-dielectric stack in a core region of the wafer;
forming a gate dielectric layer over the periphery region of the substrate;
forming a first polysilicon layer over the multi-layer dielectric-charge trapping-dielectric stack in the core region and the gate dielectric in the periphery region;
forming isolation trenches in the substrate, through the first polysilicon layer and the gate dielectric layer in the periphery region, thereby defining isolation trenches;
filling the isolation trenches with a dielectric material; and
forming a second polysilicon layer over the first polysilicon layer and the filled trenches.
9. The method of claim 8 , further comprising implanting a dopant ion species into the substrate associated with the isolation trenches after concurrently forming the isolation trenches in the core region and in the periphery region, and before filling the isolation trenches with a dielectric material.
10. The method of claim 9 , wherein the dopant ion species implanted into the substrate associated with the isolation trenches is one of a B, a BF 2 , and a p-type dopant ion species.
11. The method of claim 8 , further comprising planarizing the wafer to separate individual isolation structures after filling the isolation trenches with a dielectric material and before forming a second polysilicon layer over the first polysilicon layer and the filled trenches.
12. The method of claim 11 , wherein the planarizing the wafer to separate individual isolation structures is accomplished using a chemical mechanical polishing process.
13. The method of claim 8 , wherein the forming a multi-layer dielectric-charge trapping-dielectric stack over the substrate of the wafer comprises forming a first oxide layer overlying the substrate of the wafer, a nitride layer overlying the first oxide layer, and a second oxide layer overlying the nitride layer.
14. The method of claim 8 , wherein the shallow isolation trenches are fabricated in a multi-bit SONOS flash memory.
15. A method of fabricating a multi-bit SONOS flash memory cell, comprising:
forming a multi-layer dielectric-charge trapping-dielectric stack over a substrate of a wafer;
forming a first polysilicon layer over the multi-layer dielectric-charge trapping-dielectric stack;
concurrently forming isolation trenches in the substrate, through the first polysilicon layer and the multi-layer dielectric-charge trapping-dielectric stack, in a core region and in a periphery region, thereby defining isolation trenches;
filling the isolation trenches with a dielectric material; and
forming a second polysilicon layer over the first polysilicon layer and the filled trenches.
16. The method of claim 15 , further comprising implanting a dopant ion species into the substrate associated with the isolation trenches after concurrently forming the isolation trenches in the core region and in the periphery region, and before filling the isolation trenches with a dielectric material.
17. The method of claim 16 , wherein the dopant ion species implanted into the substrate associated with the isolation trenches is one of a B, a BF 2 , and a p-type dopant ion species.
18. The method of claim 15 , further comprising planarizing the wafer to separate individual isolation structures after filling the isolation trenches with a dielectric material and before forming a second polysilicon layer over the first polysilicon layer and the filled trenches.
19. The method of claim 18 , wherein the planarizing the wafer to separate individual isolation structures is accomplished using a chemical mechanical polishing process.
20. The method of claim 15 , wherein the forming a multi-layer dielectric-charge trapping-dielectric stack over the substrate of the wafer comprises forming a first oxide layer overlying the substrate of the wafer, a nitride layer overlying the first oxide layer, and a second oxide layer overlying the nitride layer.
21. A method of fabricating a multi-bit SONOS flash memory cell, comprising:
forming a multi-layer dielectric-charge trapping-dielectric stack over a substrate of a wafer;
removing the multi-layer dielectric-charge trapping-dielectric stack in a periphery region of the wafer, thereby defining a multi-layer dielectric-charge trapping-dielectric stack in a core region of the wafer;
forming a first polysilicon layer over the multi-layer dielectric-charge trapping-dielectric stack;
forming isolation trenches in the substrate, through the first polysilicon layer and the multi-layer dielectric-charge trapping-dielectric stack, thereby defining isolation trenches;
filling the isolation trenches with a dielectric material; and
forming a second polysilicon layer over the first polysilicon layer and the filled trenches.