Patent Assignment
Reel/Frame 036036/0738
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2015-06-30
Received: 2015-06-30
Pages: 153
Assignor
SPANSION, LLC
Executed: 2015-06-01
Assignee
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT, SAN JOSE, CA, 95134, UNITED STATES
Covered Applications
(50)
METHODS AND SYSTEMS FOR HIGH WRITE PERFORMANCE IN MULTI-BIT FLASH MEMORY DEVICES
App. No. 11/653,655
→
STORAGE DEVICE AND CONTROL METHOD THEREFOR
App. No. 11/443,770
→
CONTROL CIRCUIT AND CONTROL METHOD FOR DC-DC CONVERTER
App. No. 11/369,003
→
SIGMA-DELTA MODULATOR FOR PLL CIRCUITS
App. No. 11/363,049
→
STEP-UP (BOOST) DC REGULATOR WITH TWO-LEVEL BACK-BIAS SWITCH GATE VOLTAGE
App. No. 11/362,513
→
DC-DC CONVERTER AND METHOD FOR CONTROLLING DC-DC CONVERTER
App. No. 11/342,553
→
NON-VOLATILE MEMORY AND METHOD OF CONTROLLING THE SAME
App. No. 11/342,947
→
CLOCK GENERATION CIRCUIT AND CLOCK GENERATION METHOD
App. No. 11/312,392
→
REDUNDANCY SUBSTITUTION METHOD, SEMICONDUCTOR MEMORY DEVICE AND INFORMATION PROCESSING APPARATUS
App. No. 11/311,485
→
MEMORY ARRAY
App. No. 11/262,651
→
SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING THE SAME
App. No. 11/261,743
→
VOLTAGE SUPPLY CIRCUIT FOR MEMORY ARRAY PROGRAMMING
App. No. 11/250,913
→
RELIABLE AND SCALABLE VIRTUAL GROUND MEMORY ARRAY FORMED WITH REDUCED THERMAL CYCLE
App. No. 11/242,773
→
FLASH MEMORY PROGRAMMING USING AN INDICATION BIT TO INTERPRET STATE
App. No. 11/229,664
→
MEMORY DEVICES WITH ACTIVE AND PASSIVE DOPED SOL-GEL LAYERS
App. No. 11/228,842
→
SEMICONDUCTOR MEMORY DEVICE USING READ DATA BUS FOR WRITING DATA DURING HIGH-SPEED WRITING
App. No. 11/228,777
→
VARIABLE CAPACITY CIRCUIT AND CONTROL METHOD OF VARIABLE CAPACITY CIRCUIT
App. No. 11/216,000
→
NON-VOLATILE MEMORY DEVICE, AND CONTROL METHOD THEREFOR
App. No. 11/215,850
→
EXPOSURE SYSTEM, SEMICONDUCTOR DEVICE, AND METHOD FOR FABRICATING THE SEMICONDUCTOR DEVICE
App. No. 11/215,246
→
NON-VOLATILE MEMORY DEVICE AND ERASING METHOD THEREFOR
App. No. 11/215,889
→
FLASH MEMORY DEVICE HAVING IMPROVED PROGRAM RATE
App. No. 11/212,850
→
BACK-TO-BACK NPN/PNP PROTECTION DIODES
App. No. 11/194,449
→
SEMICONDUCTOR MEMORY WITH DATA RETENTION LINER
App. No. 11/195,201
→
PROGRAMMING A MEMORY DEVICE
App. No. 11/174,560
→
MEMORY SYSTEM AND TEST METHOD THEREFOR
App. No. 11/173,735
→
METHOD OF PROGRAMMING A RESISTIVE MEMORY DEVICE
App. No. 11/166,572
→
RESISTIVE MEMORY DEVICE WITH IMPROVED DATA RETENTION
App. No. 11/165,005
→
SYSTEM AND METHOD FOR REDUCING PROCESS-INDUCED CHARGING
App. No. 11/146,126
→
METHOD OF PROGRAMMING A MEMORY DEVICE
App. No. 11/146,690
→
PAGE BUFFER ARCHITECTURE FOR PROGRAMMING, ERASING AND READING NANOSCALE RESISTIVE MEMORY DEVICES
App. No. 11/139,227
→
CARRIER FOR STACKED TYPE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
App. No. 11/126,739
→
SELF-ALIGNED STI SONOS
App. No. 11/113,509
→
NON-CRITICAL COMPLEMENTARY MASKING METHOD FOR POLY-1 DEFINITION IN FLASH MEMORY DEVICE FABRICATION
App. No. 11/099,339
→
MEMORY DEVICE WITH IMPROVED DATA RETENTION
App. No. 11/089,707
→
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE THAT ERASES STORED DATA AFTER A PREDETERMINED TIME PERIOD WITHOUT THE USE OF A TIMER CIRCUIT
App. No. 11/087,735
→
AUTOMATED TESTS FOR BUILT-IN SELF TEST
App. No. 11/041,608
→
METHOD FOR CONTROLLING POLY 1 THICKNESS AND UNIFORMITY IN A MEMORY ARRAY FABRICATION PROCESS
App. No. 11/035,188
→
VARIABLE DENSITY AND VARIABLE PERSISTENT ORGANIC MEMORY DEVICES, METHODS, AND FABRICATION
App. No. 11/034,071
→
METHOD, SYSTEM, AND CIRCUIT FOR PERFORMING A MEMORY RELATED OPERATION
App. No. 11/001,940
→
CIRCUIT AND METHOD FOR CONTROLLING DC-DC CONVERTER
App. No. 10/981,792
→
VOLTAGE CONTROLLED OSCILLATOR AND PLL CIRCUIT
App. No. 10/939,513
→
SYSTEMS AND METHODS FOR ADJUSTING PROGRAMMING THRESHOLDS OF POLYMER MEMORY CELLS
App. No. 10/919,846
→
FLASH MEMORY DEVICE
App. No. 10/838,215
→
METHOD FOR MINIMIZING FALSE DETECTION OF STATES IN FLASH MEMORY DEVICES
App. No. 10/838,962
→
MEMORY DEVICE AND METHODS OF USING AND MAKING THE DEVICE
App. No. 10/818,261
→
AVOIDING FIELD OXIDE GOUGING IN SHALLOW TRENCH ISOLATION (STI) REGIONS
App. No. 10/799,413
→
TESTING FOR OPERATING LIFE OF A MEMORY DEVICE WITH ADDRESS CYCLING USING A GRAY CODE SEQUENCE
App. No. 10/791,417
→
ACTIVE PROGRAMMING AND OPERATION OF A MEMORY DEVICE
App. No. 10/776,870
→
STRUCTURE AND METHOD FOR LOW VSS RESISTANCE AND REDUCED DIBL IN A FLOATING GATE MEMORY CELL
App. No. 10/762,445
→
FLASH MEMORY WITH BURIED BIT LINES
App. No. 10/738,322
→