Reliable and scalable virtual ground memory array formed with reduced thermal cycle
View Patent ↗According to one exemplary embodiment, a method of fabricating a virtual ground memory array includes forming a number of polysilicon segments on a gate dielectric layer, where the gate dielectric layer is situated on a substrate. The method further includes forming a number of bitlines in the substrate, where each of the bitlines is situated adjacent to at least one of the polysilicon segments, and where the bitlines are formed after the polysilicon segments. The method further includes forming a gap-filling dielectric segment over each of the bitlines. The method can further include removing the masking layer and a portion of the gap-filling dielectric segment, depositing an interpoly dielectric layer on the polysilicon segments and on a remaining portion of the gap-filling dielectric segment, and forming a second polysilicon layer on the interpoly dielectric layer.
1. A method for fabricating a virtual ground memory array, said method comprising steps of:
forming a plurality polysilicon segments on a gate dielectric layer, said gate dielectric layer being situated on a substrate;
forming a plurality of bitlines in said substrate, each of said plurality of bitlines being situated adjacent to at least one of said plurality of polysilicon segments;
forming a gap-filling dielectric segment over said each of said plurality of bitlines, said gap-filling dielectric segment being situated on said gate dielectric layer;
wherein said step of forming said plurality of bitlines in said substrate is performed after said step of forming said plurality of polysilicon segments on said gate dielectric layer, and wherein said virtual ground memory array is a virtual ground floating gate memory array.
2. The method of claim 1 wherein said virtual ground floating gate memory array is a virtual ground floating gate flash memory array.
3. The method of claim 1 wherein said step of forming said plurality polysilicon segments on said gate dielectric layer comprises steps of:
depositing a first polysilicon layer over said gate dielectric layer;
depositing a masking layer over said first polysilicon layer;
patterning and etching said masking layer and said first polysilicon layer;
removing said masking layer and a portion of said gap-filling dielectric segment;
depositing an interpoly dielectric layer on said plurality of polysilicon segments and on a remaining portion of said gap-filling dielectric segment.
4. The method of claim 3 further comprising a step of forming a second polysilicon layer over said interpoly dielectric layer.
5. A method for fabricating a virtual ground memory array, said method comprising steps of:
forming a first plurality of polysilicon segments on a gate dielectric layer, said gate dielectric layer being situated on a substrate;
forming a plurality of bitlines in said substrate, each of said plurality of bitlines being situated adjacent to at least one of said first plurality of polysilicon segments;
forming a gap-filling dielectric layer over said first plurality of polysilicon segments and said gate dielectric layer;
planarizing said gap-filling dielectric layer to form a plurality of gap-filling dielectric segments, each of said plurality of gap-filling dielectric segments being situated over one of said plurality of bitlines and on said gate dielectric layer;
wherein said step of forming said plurality of bitlines in said substrate is performed after said step of forming said first plurality of polysilicon segments on said gate dielectric layer, and wherein said virtual ground memory array is a virtual ground floating gate memory array.
6. The method of claim 5 wherein said virtual ground floating gate memory array is a virtual ground floating gate flash memory array.