Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell
View Patent ↗According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.
1. A floating gate memory cell situated on a substrate, said floating gate memory cell comprising:
a stacked gate structure situated on said substrate, said stacked gate structure being situated over a channel region in said substrate;
a recess formed in said substrate adjacent to said stacked gate structure, said recess having a sidewall, a bottom, and a depth;
a source of said floating gate memory cell situated adjacent to said sidewall of said recess and under said stacked gate structure;
a Vss connection region situated under said bottom of said recess and under said source, said Vss connection region being connected to said source, said Vss connection region being a heavily doped region to reduce a Vss resistance;
wherein said Vss connection region being situated under said bottom of said recess causes said source to have a reduced lateral diffusion in said channel region, thereby preventing an increase in a drain induced barrier lowering.
2. The floating gate memory cell of claim 1 wherein said reduced lateral diffusion of said source causes a reduction in drain induced barrier lowering in said floating gate memory cell.
3. The floating gate memory cell of claim 1 wherein said sidewall of said recess is substantially perpendicular to a top surface of said substrate.
4. The floating gate memory cell of claim 1 wherein said depth of said recess is between approximately 200.0 Angstroms and approximately 500.0 Angstroms.
5. The floating gate memory cell of claim 1 wherein said stacked gate structure comprises an ONO stack situated on a floating gate.
6. The floating gate memory cell of claim 1 wherein said floating gate memory cell is a NOR-type floating gate flash memory cell.
7. A floating gate memory cell situated on a substrate, said floating gate memory cell comprising a stacked gate structure situated on said substrate, said stacked gate structure being situated over a channel region in said substrate, a recess formed in said substrate adjacent to said stacked gate structure, said recess having a sidewall, a bottom, and a depth, said floating gate memory cell being characterized in that:
a source of said floating gate memory cell is situated adjacent to said sidewall of said recess and under said stacked gate structure, a Vss connection region is situated under said bottom of said recess and under said source, said Vss connection region being connected to said source, said Vss connection region being a heavily doped region to reduce a Vss resistance, wherein said Vss connection region being situated under said bottom of said recess causes said source to have a reduced lateral diffusion in said channel region, thereby preventing an increase in a drain induced barrier lowering.
8. The floating gate memory cell of claim 7 wherein said reduced lateral diffusion of said source causes a reduction in drain induced barrier lowering in said floating gate memory cell.
9. The floating gate memory cell of claim 7 wherein said sidewall of said recess is substantially perpendicular to a top surface of said substrate.
10. The floating gate memory cell of claim 7 wherein said depth of said recess is between approximately 200.0 Angstroms and approximately 500.0 Angstroms.
11. The floating gate memory cell of claim 7 wherein said stacked gate structure comprises an ONO stack situated on a floating gate.
12. The floating gate memory cell of claim 7 wherein said floating gate memory cell is a NOR-type floating gate flash memory cell.