Non-volatile memory and method of controlling the same
A single cell that has a gate insulating film formed with an ONO film is provided in a region in which two bit lines cross one word line. The single cell is a four-bit multi-value cell, and has four charge accumulation regions. Two plug-like control electrodes are provided in the region surrounded by the word line and the bit lines. A bias is applied to one of the plug-like control electrodes and the word line so that the portion on the surface of the semiconductor substrate that is located immediately below the word line and corresponds to the location of the bias-applied control electrode is put into an accumulation state or a depletion state. In this manner, the width of the channel is adjusted, and the charge holding state of each of the four charge accumulation regions is controlled through the channel width adjustment.
1. A non-volatile memory comprising:
a gate insulating film that includes an ONO film having a first oxide film, a nitride film, and a second oxide film stacked in this order on a semiconductor substrate; and
control electrodes that are provided on both sides of a gate electrode of each memory cell, wherein a channel region formed between the control electrodes has a channel width less than half of a width of the gate electrode.
2. The non-volatile memory as claimed in claim 1 , wherein each memory cell has four charge accumulation regions located below the gate electrode, and the four charge accumulation regions are arranged in rows and columns.
3. The non-volatile memory as claimed in claim 2 , wherein the memory cells are arrayed in a first direction and a second direction, the non-volatile memory further comprising word lines and bit lines running in the first direction and the second direction respectively, wherein the word lines provide gate electrodes of the memory cells aligned in the first direction and the bit lines provide sources and drains of the memory cells aligned in the second direction.
4. A non-volatile memory comprising:
a gate insulating film that includes an ONO film having a first oxide film, a nitride film, and a second oxide film stacked in this order on a semiconductor substrate; and
control electrodes that are provided on both sides of a gate electrode of each memory cell, wherein the memory cells are arrayed in a first direction and a second direction, the non-volatile memory further comprising word lines and bit lines running in the first direction and the second direction respectively, wherein the word lines provide the gate electrodes of the memory cells aligned in the first direction and the bit lines provide sources and drains of the memory cells aligned in the second direction, wherein the bit lines are embedded in the semiconductor substrate.
5. The non-volatile memory as claimed in claim 4 , wherein each of the control electrodes is provided in a region defined by two adjacent word lines and two adjacent bit lines.
6. The non-volatile memory as claimed in claim 4 , wherein the control electrodes are arranged in rows and columns.
7. The non-volatile memory as claimed in claim 1 , wherein the gate electrode and the control electrodes are supplied with such voltages that the channel width becomes less than half the width of the gate electrode.
8. The non-volatile memory as claimed in claim 1 , wherein:
the gate electrode is supplied with a voltage equal to or higher than a threshold voltage so that a region in the semiconductor substrate located below the gate insulating film serves as the channel region;
one of the control electrodes is supplied with a control voltage so that a region in the semiconductor substrate in the vicinity of said one of the control electrodes is an accumulation region; and
a depletion region formed in the semiconductor substrate and located between the accumulation region and the channel region defines the channel width.
9. The non-volatile memory as claimed in claim 8 , wherein conditions for biasing the sources and drains are alternately switched so that write and read operations are performed.
10. The non-volatile memory as claimed in claim 1 , wherein the gate electrodes are made of polysilicon.
11. The non-volatile memory as claimed in claim 1 , wherein:
the semiconductor substrate is of a P-conduction type; and
the gate electrode receives a positive bias voltage, and the control electrodes receive negative bias voltages.
12. The non-volatile memory as claimed in claim 1 , wherein:
the semiconductor substrate is of an N-conduction type; and
the gate electrode receives a negative bias voltage, and the control electrodes receive positive bias voltages.
13. A method for controlling a non-volatile memory having an ONO film on a semiconductor substrate, the method comprising the steps of:
applying a voltage to a gate electrode that is shared among memory cells; and
applying another voltage to one of two control electrodes between which the gate electrode is interposed,
wherein four charge accumulation regions are formed in a nitride film of the ONO film in a region that is located below the gate electrode and is interposed between the two control electrodes.
14. The method as claimed in claim 13 , wherein:
the step of applying a voltage to the gate electrode includes applying a positive voltage to the gate electrode; and
the step of applying another voltage to one of the two control electrodes includes applying a negative voltage to said one of the two control electrodes.
15. The method as claimed in claim 13 , wherein:
the step of applying a voltage to the gate electrode includes applying a negative voltage to the gate electrode; and
the step of applying another voltage to one of the two control electrodes includes applying a positive voltage to said one of the two control electrodes.
16. The non-volatile memory as claimed in claim 1 , wherein each of the control electrodes is provided in a region defined by two adjacent word lines and two adjacent bit lines.
17. The non-volatile memory as claimed in claim 1 , wherein the control electrodes are arranged in rows and columns.
18. The non-volatile memory as claimed in claim 1 , wherein a charge accumulation region in the nitride film interposed between the control electrodes is operatively divided into four parts.