Non-volatile memory device, and control method therefor
View Patent ↗During an erase operation, lower decoder groups 20 ( i ) and 21 ( i ) (i=1 to m) of erase-target sectors are connected, at their respective low voltage power supply terminals (VL), to a first negative voltage supply line (VM) via switches (B) ( 50 and 51 , respectively) and a negative bias voltage is supplied to local word lines. The first negative voltage supply line (VM) is connected to a level shift circuit ( 4 ), and is level-shifted to a voltage at a higher level relative to that of a second negative voltage (VMP) which is output from a negative voltage generator circuit ( 3 ) via a second negative voltage supply line (VMP). An upper decoder group ( 10 ) is connected, at its low voltage power supply terminal (VL), to the second negative voltage line (VMP) via a switch (A) ( 5 ). All global word lines GWL 0 ( i ) (i=0 to m) are biased to the second negative voltage (VMP) by an active signal (ACTB 0 ( i )) at high level supplied to the upper decoder group ( 10 ) and are biased to a lower voltage level relative to the first negative voltage (VM) as a bias voltage to the local word lines.
1. A non-volatile memory device comprising:
a first N-type transistor arranged between a first terminal and a word line, the first N-type transistor supplying the word line a positive voltage supplied to the first terminal in a manner of electrical conduction;
a negative voltage generator section for generating a first negative voltage and for supplying a control terminal of the first N-type transistor a second negative voltage the level of which is lower than the first negative voltage; and
a second N-type transistor arranged between a second terminal and the word line, the second N-type transistor discharging the positive voltage supplied to the word line by electrical conduction,
wherein supply of the first negative voltage to the word line is conducted on condition that the second N-type transistor becomes conductive and the first negative voltage is supplied to the second terminal.
2. A non-volatile memory device according to claim 1 further comprising a third N-type transistor arranged between a third terminal and the control terminal of the first N-type transistor, the third N-type transistor discharging bias voltage supplied to the control terminal by electrical conduction,
wherein supply of the second negative voltage to the control terminal is conducted on condition that the third N-type transistor becomes conductive and the second negative voltage is supplied to the third terminal.