Granted Patent B1

US 7,307,878 · App. 11/212,850 · Granted Dec 11, 2007

Abstract

Claims (38)

1. A method of programming a non-volatile memory device including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, comprising:

receiving a programming window that identifies a plurality of memory cells in the array;

identifying a first group of memory cells to be programmed from the plurality of memory cells;

programming the first group of memory cells;

verifying a programming state of the first group of memory cells;

writing values indicative of the programmed state of the first group of memory cells to a buffer;

identifying a second group of memory cells to be programmed based on the values in the buffer; and

programming the second group of memory cells.

2. The method of claim 1 , wherein the buffer includes an array for storing the programmed state of the first group of memory cells.

3. The method of claim 1 , wherein the plurality of memory cells includes 2,048 memory cells.

4. The method of claim 1 , wherein the verifying includes:

determining whether each memory cell in the first group of memory cells is programmed; and wherein the method further comprises:

reprogramming any memory cells in the first group of memory cells that are not programmed.

5. The method of claim 1 , wherein the verifying comprises simultaneously verifying a programming state for up to 2,048 memory cells.

6. The method of claim 1 , wherein the array of memory cells include SONOS (silicon-oxide-nitride-oxide-silicon) type NOR memory cells.

7. The method of claim 1 , wherein the charge storage element comprises a dielectric charge storage element configured to store at least two independent charges for each memory cell.

8. The method of claim 1 , wherein the programming comprises:

applying a first voltage to the control gate; and

applying a second voltage to the drain region.

9. The method of claim 8 , where the verifying comprises:

applying a third voltage to the control gate; and

monitoring a threshold voltage in the first group of memory cells.

10. The method of claim 9 , wherein the third voltage is different from the first voltage.

11. A memory device comprising:

at least one array of non-volatile memory cells, the at least one array comprising:

a plurality of bit lines each connected to source or drain regions of a plurality of the memory cells; and

a plurality of word lines, arranged orthogonally to the bit lines, each word line being connected to gate regions of a plurality of the memory cells;

a voltage supply component configured to generate programming and verifying voltages for programming and verifying the programming of a plurality of the memory cells;

first control logic configured to program memory cells within the at least one array of non-volatile memory cells corresponding to a programming window identifying a group of memory cells to be programmed;

a plurality of sense amplifiers operatively connected to the plurality of bit lines;

second control logic configured to verify a programming state of the group of memory cells by monitoring the programming state for each of the group of memory cells using the plurality of sense amplifiers; and

a verify buffer configured to store values indicative of the programming states for each of the group of memory cells.

12. The memory device of claim 11 , wherein the programming window corresponds to the memory cells along a selected word line.

13. The memory device of claim 11 , further comprising:

third control logic configured to identify non-programmed memory cells from the group of memory cells based on the values stored in the verify buffer; and

fourth control logic configured to program the non-programmed memory cells.

14. The memory device of claim 11 , wherein the programming and verifying voltages are different voltages.

15. The memory device of claim 11 , wherein the at least one array of non-volatile memory cells include multi-bit SONOS (silicon-oxide-nitride-oxide-silicon) type NOR memory cells.

Assignments (9)