Exposure system, semiconductor device, and method for fabricating the semiconductor device
View Patent ↗In order to link a defect inspection process before forming contact holes with an exposure process for forming the contact holes, a position (physical coordinates) of a defect on a wafer is stored, the defect having been detected in the defect inspection process before forming the contact holes, an exposure (dummy exposure) is performed under the condition that no contact hole is formed on the above-mentioned position. In this method, no contact hole is formed in the region having the defect therein, the cell is considered as a defective one, yet a word line (control gate) and a bit line are not short-circuited through the contact hole, and makes it possible to avoid the short-circuiting by only applying a redundancy to the bit line as conventionally employed.
1. An exposure system comprising:
inspection equipment that detects a defect on a semiconductor wafer;
a controller that stores physical coordinates of the defect on the semiconductor wafer; and
an exposure device that exposes the semiconductor wafer under an exposure condition controlled by the controller to form contact holes so that no contact hole is formed in a region corresponding to the physical coordinates of the defect.
2. The exposure system as claimed in claim 1 , wherein the exposure device is an electron beam exposure device of a scanner type.
3. An exposure system comprising:
inspection equipment that detects a defect on a semiconductor wafer;
a controller that stores physical coordinates of the defect on the semiconductor wafer; and
an exposure device that exposes the semiconductor wafer under an exposure condition controlled by the controller so that no contact hole is formed in a region corresponding to the physical coordinates of the defect, wherein the exposure device exposes the region under a defocused condition or irradiates no beam onto the region.
4. A method of fabricating a semiconductor device comprising the steps of:
detecting a defect on a semiconductor wafer in advance of forming contact holes;
storing physical coordinates of the defect detected;
exposing the semiconductor wafer to form the contact holes so that no contact hole is formed in a region corresponding to the physical coordinates of the defect.
5. The method as claimed in claim 4 , further comprising a step of replacing a bit line that includes the region having the defect with a redundant bit line.
6. The method as claimed in claim 4 , wherein the step of exposing exposes the semiconductor wafer under a defocused condition or irradiates no beam onto the region.
7. The method as claimed in claim 6 , wherein the step of exposing forms the contact holes so as to make a memory cell arrangement of a NOR type.