Memory device having improved periphery and core isolation
View Patent ↗The present invention discloses a memory device having an improved periphery isolation region and core isolation region. A first trench is formed in a core region. Substrate material bordering the first trench is then oxidized to form a first liner. The first liner is then removed. A second trench is then formed in a periphery region. A second oxidation is then performed such that a second liner is formed from the substrate material bordering the first and second trenches. A dielectric trench fill having substantially uniform density is then deposited in the first and second trenches.
1. A method of fabricating a flash memory comprising:
forming a first trench in a first region, wherein said first trench has a first depth;
forming a first liner oxide in said first trench;
forming a second trench in a second region subsequent to said forming said first liner oxide, wherein said second trench has a second depth, wherein said second depth is not equal to said first depth;
removing said first liner oxide;
subsequent to said removing said first liner oxide, forming a second liner oxide in said first trench and said second trench, wherein said second liner oxide provides for corner rounding of said second trench and double corner rounding of said first trench; and
depositing a dielectric in said first trench and said second trench.
2. The method according to claim 1 , wherein said removing said first liner oxide increases an aspect ratio of said first trench.
3. The method according to claim 1 , wherein said removing said first liner oxide provides for said dielectric having substantially uniform density.
4. The method according to claim 1 , wherein said first liner oxide provides for corner rounding of said first trench.
5. The method according to claim 4 , wherein said corner rounding of said first trench provides for said dielectric having substantially uniform density.
6. The method according to claim 4 , wherein said corner rounding of said first trench reduces corner effects of said first trench.
7. The method according to claim 1 , wherein said double corner rounding of said first trench reduces corner effects of said first trench, and said corner rounding of said second trench reduces corner effects of said second trench.
8. The method according to claim 1 , wherein said first region is a core region and said second region is a periphery region.
9. The method according to claim 1 , wherein said first region is a periphery region and said second region is a core region.
10. A method of fabricating a memory device comprising:
etching a core trench to a first depth;
oxidizing a substrate material proximate said core trench, wherein a first liner oxide layer is formed;
etching a periphery trench to a second depth subsequent to oxidizing said substrate material proximate said core trench, wherein said first depth and second depth are different;
removing said first liner oxide layer;
subsequent to said removing said first liner oxide, oxidizing said substrate material proximate said core trench and said periphery trench, wherein a second liner oxide layer is formed and wherein a corner of said core trench is rounded and a corner of said periphery trench is double rounded; and
depositing a trench fill in said core trench and said periphery trench.
11. The method according to claim 10 , wherein said corner rounding of said core trench provides for reducing a thickness of said second liner oxide.