IP Library Granted Patent US 6,888,763
Granted Patent B1
US 6,888,763 · App. 10/358,498 · Granted May 3, 2005

Compensated oscillator circuit for charge pumps

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Quick Facts
Patent No.
US 6,888,763
App. No.
10/358,498
Granted
May 3, 2005
Kind
B1
Abstract

A charge pump oscillator circuit with compensation for variations in process and operating environment. The charge pump oscillator is designed with a rolloff characteristic that enables operation at both weak and strong process corners without excessive power consumption. Composite resistors in the oscillator circuit are composed of component resistors that are fabricated with different processes, e.g., implant and deposition. The resistance of the composite resistor is thus in order to provide compensation for variations in processing and operating environment. The composite resistor may be used as a feedback loop resistor, or may be used as a source degenerate resistor to control the supply current to the oscillator.

Claims (22)

1. A charge pump circuit for a non-volatile memory integrated circuit comprising an oscillator circuit, wherein said oscillator circuit comprises a composite resistor to provide compensation for fabrication process variations and variations in an operational environment.

2. The charge pump circuit of claim 1 , wherein said oscillator circuit comprises at least one transistor coupled to a supply voltage (V cc ) by said composite resistor.

3. The charge pump circuit of claim 2 , wherein said composite resistor comprises a first resistor having a positive temperature coefficient of resistance and second resistor having a negative temperature coefficient of resistance.

4. The charge pump circuit of claim 2 , wherein said oscillator comprises a complementary transistor coupled to ground by said composite resistor.

5. The charge pump circuit of claim 2 , wherein the ratio between the value of the composite resistor to a value of an on resistance of said transistor increases with decreasing temperature over the temperature range of +100° C. to −40° C.

6. The charge pump circuit of claim 5 , wherein the ratio between the value of the composite resistor to a value of an on resistance of said transistor increases with decreasing temperature over the temperature range of +100° C. to +25° C.

7. The charge pump circuit of claim 2 , wherein said composite resistor comprises a first implanted resistor and a second deposited resistor.

8. The charge pump circuit of claim 7 , wherein said first resistor is an n-well resistor and said second resistor is a polysilicon resistor.

9. The charge pump circuit of claim 1 , wherein said oscillator circuit comprises a Schmitt trigger.

10. The charge pump circuit of claim 9 , wherein said oscillator circuit comprises a composite source degenerate resistor and a composite feedback loop resistor.

11. A flash memory device comprising:

an array of capacitors coupled by switches;

an oscillator circuit coupled to said array of capacitors, said oscillator circuit comprising a first resistor having a positive temperature coefficient of resistance, and a second resistor having a negative temperature coefficient of resistance.

12. The flash memory device of claim 11 , wherein said first resistor and said second resistor are connected in series.

13. The flash memory device of claim 12 wherein the net temperature coefficient of resistance is positive.

14. The flash memory device of claim 12 , wherein said first resistor and said second resistor are coupled to an input and an output of said oscillator circuit to provide a feedback current.

15. The flash memory device of claim 14 , wherein said implanted resistor is an n-well resistor.

16. The flash memory device of claim 15 , further comprising a feedback loop resistor and a source degenerate resistor.

17. The flash memory device of claim 14 , wherein said deposited resistor is a polysilicon resistor.

18. The flash memory device of claim 12 , wherein said oscillator circuit comprises a transistor coupled to one of said first resistor and said second resistor.

19. The flash memory device of claim 11 , wherein one of said first and second resistors is an implanted resistor and one of said first and second resistors is a deposited resistor.

20. The flash memory device of claim 11 , wherein said oscillator comprises a Schmitt trigger.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2022
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES LLC
Reel/Frame 059721/0467 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036036/0001 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →