Granted Patent B1

US 6,897,110 · App. 10/305,750 · Granted May 24, 2005

Abstract

Claims (69)

1. A method of fabricating a memory array, comprising:

a) partially forming said memory array during a first formation stage comprising:

i) forming a plurality of bitlines in a substrate, wherein said bitlines comprise source/drain regions of memory cells;

ii) forming a plurality of data storage regions above said bitlines;

iii) forming a plurality of wordlines above said data storage regions, wherein said wordlines comprise gate regions of said memory cells;

iv) forming a first metal region above a first of said bitlines and coupled to said first bitline; and

v) forming a second metal region that is not electrically coupled to said first metal region, wherein an antenna ratio between said first of said bitlines and said first metal region is lower than if said first and second metal regions were electrically coupled; and

b) forming an electrical coupling between said first metal region to said second metal region after said first formation stage, wherein said second metal region does not contribute to charge damage to said data storage regions during said first formation stage.

2. The method of claim 1 , wherein said partially forming said memory array further comprises:

forming a diode between said substrate and said portion of said metal region that is coupled to said first bitline.

3. The method of claim 2 , wherein said partially forming said memory array further comprises:

forming a fuse between said first bitline and one of said wordlines to prevent charge from damaging ones of said plurality of data storage regions during fabrication; and

blowing said fuse.

4. The method of claim 1 , wherein said partially forming said memory array further comprises:

fabricating a fuse between said substrate and said portion of said metal layer that is electrically coupled to said first bitline to prevent damage to a data storage region of said plurality of data storage regions that is under a wordline of said plurality of wordlines near said coupling of said first metal region to said first bitline; and

blowing said fuse.

5. The method of claim 4 , wherein said partially forming said memory array further comprises:

fabricating a fuse between said first bitline and a first of said wordlines to prevent charge from damaging a first of said plurality of data storage regions and which is under said first wordline during fabrication; and

blowing said fuse.

6. The method of claim 1 , wherein said partially forming said memory array further comprises:

fabricating a fuse between said first bitline and one of said wordlines to prevent charge from damaging a first of said plurality of data storage regions associated with said one wordline during fabrication; and

blowing said fuse.

7. The method of claim 1 , wherein said partially forming said memory array further comprises:

fabricating a diode between said first bitline and one of said wordlines to prevent charge from damaging a first of said plurality of data storage regions during fabrication.

8. A method of protecting a memory array during fabrication, said method comprising the steps of:

forming a first and a second region in a substrate, said first and a second regions operable to function as sources or drains;

forming a third region operable to store a charge above said first and a second regions;

forming a fourth region above said third region, said fourth region operable to function as gates, wherein portions of said first, second, third, and fourth regions form a memory cell operable to store charge in two locations in said third region;

forming a metal region above said fourth region and coupled to one of said first and second regions;

forming a fuse between said metal region and said substrate to prevent excessive charge from damaging said third region during fabrication; and

blowing said fuse.

9. The method of claim 8 further comprising the step of:

forming an electrical coupling between a second metal region and said metal region coupled to said one of said first and second regions.

10. The method of claim 8 further comprising the step of:

forming a second fuse between said first region and said second region; and

blowing said second fuse.

11. A method of protecting a memory array during fabrication, said method comprising the steps of:

forming a first plurality of regions in a substrate, said regions operable to function as sources or drains;

forming a second plurality of regions above first plurality, said second plurality operable to function as data storage regions;

forming a third plurality of regions above second plurality, said third plurality operable to function as gates;

forming a metal region above said third plurality of regions and coupled to one of said first plurality of regions;

forming a diode between said metal region and said substrate to prevent excessive charge from damaging one of said data storage regions during fabrication.

12. The method of claim 11 further comprising the steps of:

forming a second metal region; and

forming an electrical coupling between said second metal region and said metal region above said third plurality of regions.

13. The method of claim 11 , further comprising the step of:

forming a diode between one of said first plurality of regions and one of said third plurality of regions.

14. A method of protecting a memory array during fabrication, said method comprising the steps of:

forming a pair of source/drain regions in a substrate;

forming a storage region above said source/drain regions and comprising a nitride region between two insulating regions, wherein said storage region is operable to store charge in two locations;

forming a gate region above said storage region;

forming a metal region coupled to one region of said pair of source/drain regions;

forming a fuse between said gate region and said one of said pair of source/drain regions to prevent charge from damaging said storage region during fabrication; and

blowing said fuse.

15. The method of claim 14 further comprising the step of:

completing said metal region by forming a remaining portion of said metal region and coupling said remaining portion of said metal region to said metal region coupled to said one region of said pair of source/drain regions.

16. The method of claim 14 further comprising the step of:

forming a second fuse between said metal region and said substrate; and

blowing said second fuse.

17. A method of protecting a memory array during fabrication, said method comprising the steps of:

forming a plurality of bitlines in a substrate, each bitline comprising source/drain regions;

forming a data storage region comprising a nitride region between two insulating regions, wherein said data storage region is operable to store charge in two locations;

forming a plurality of wordlines above said data storage region and comprising gate regions;

forming a metal region coupled to a first of said plurality of bitlines;

forming a diode between said first bitline and a first of said plurality of wordlines to prevent charge from damaging said data storage region during fabrication.

18. The method of claim 17 further comprising the step of:

completing said metal region by forming a remaining portion of said metal region and coupling said remaining portion of said metal region to said metal region coupled to said first bitline.

19. The method of claim 17 further comprising the step of:

forming a diode between said metal region and said substrate.

Assignments (11)