Memory device and method
View Patent ↗A memory device and a method for refreshing the memory device. The memory device includes a memory cell capable of storing two bits of data. One bit is referred to as the normal data bit and the other bit is referred to as the complementary data bit. Each memory cell has an associated dynamic reference cell. The normal data is refreshed by latching refresh data into a data latch and ORing the latched data with input data. The refresh data is written to the corresponding memory location. The data for the complementary data bit is refreshed by latching complementary data bit refresh data into the complementary data latches and writing to the memory cell. The normal and complementary data bits are refreshed before each read operation.
1. A method for refreshing a memory device, comprising:
providing a memory cell having first and second memory locations;
generating a first updated latch value for a normal bit of a byte;
writing the first updated latch value to the first memory location during a clock cycle;
generating a second updated latch value for a complementary bit of a byte; and
writing the second updated latch value to the second memory location during a subsequent clock cycle.
2. The method of claim 1 , wherein generating the first updated latch value includes performing a logic operation on a value of the first memory location and a first data value.
3. The method of claim 2 , wherein generating the second updated latch value includes performing a logic operation on a value of the second memory location and a second data value.
4. The method of claim 2 , wherein performing the logic operation includes ORing the value of the first memory location and the first data value.
5. The method of claim 4 , wherein generating the second updated latch value includes performing a logic operation on a value of the second memory location and a second data value.
6. The method of claim 5 , wherein performing the logic operation includes ORing the value of the second memory location and the second data value.
7. The method of claim 1 , wherein writing the first updated latch value to the first memory location includes latching the first updated latch value in response to at least one control signal.
8. The method of claim 7 , wherein the at least one control signal comprises a first control signal indicative of a value of a first data value and a second control signal indicative of a status of a read operation.
9. The method of claim 8 , wherein writing the second updated latch value to the second memory location includes latching the second updated latch value in response to at least one control signal.
10. The method of claim 9 , wherein the at least one control signal comprises a first complementary control signal indicative of a value of the second data value and a second complementary control signal indicative of a status of the read operation.
11. A method for operating a memory device, comprising:
refreshing a normal bit of a byte stored in the memory device during a clock cycle; and
refreshing a complementary bit of the byte stored in the memory device during a different clock cycle.
12. The method of claim 11 , wherein refreshing the normal bit comprises:
receiving first and second control signals at a first latch of the memory device;
latching a logic value of the normal bit at a first node in response to the first and second control signals;
generating a first update value by performing a logic function on the logic value and a first data value; and
transmitting the first update value of the normal bit to an output terminal of the first latch in response to a third control signal.
13. The method of claim 12 , further including transmitting the first update value of the normal bit to an output terminal of a second latch in response to a fourth control signal.
14. The method of claim 13 , wherein refreshing the complementary bit comprises:
receiving the first and fifth control signals at a second latch of the memory device;
latching a second update value of the complementary bit at a second node in response to the first and fifth control signals; and
transmitting the second update value of the complementary bit to an output terminal of the second latch in response to a sixth control signal.
15. The method of claim 11 , wherein the different clock cycle is a subsequent clock cycle.
16. The method of claim 11 , wherein the clock cycle is a subsequent clock cycle.
17. A method for refreshing a memory device, comprising:
providing the memory device having a data latch, a complementary data latch, and a write latch;
applying first and second control signals to the data latch, wherein the first control signal represents a programming status of a memory location;
latching a memory value in the data latch in response to the first and second control signals;
performing a logic operation on the memory value and a data value to generate a refresh value;
transmitting the refresh value to an output terminal of the write latch;
applying the first control signal and a third control signal to the complementary data latch;
latching a complementary refresh value in the complementary data latch in response to the first control signal and a third control signal; and
transmitting the complementary refresh value to the output terminal of the write latch.
18. The method of claim 17 , wherein performing the logic operation on the memory value and the data value includes ORing the memory value and the data value to generate the refresh value.
19. The method of claim 18 , further including transmitting the refresh value at the first node of the data latch to an output terminal of the data latch in response to a fourth control signal.
20. The method of claim 19 , further including transmitting the logic low level at the first node of the data latch to an output terminal of the write latch in response to a fifth control signal.
21. The method of claim 20 , wherein applying the first and third control signals produces a logic low level at a first node of the complementary data latch.
22. The method of claim 21 , further including transmitting the logic low level at the first node of the complementary data latch to the output terminal of the data latch in response to the fourth control signal.
23. The method of claim 22 , further including transmitting the logic low level at the first node of the complementary data latch to the output terminal of the write latch in response to the fifth control signal.
24. The method of claim 23 , wherein the logic low level at the first node of the data latch is produced during the first half of a first clock cycle, the logic low level at the first node of the data latch is transmitted to the output terminal of the write latch during a second half of the first clock cycle, the logic low level at the first node of the complementary data latch is produced during the first half of a second clock cycle, and the logic low level at the first node of the complementary data latch is transmitted to the output terminal of the write latch during a second half of the second clock cycle.