Simultaneous execution command modes in a flash memory device
View Patent ↗A method for operating a flash memory includes, in response to a received operation command, initiating an embedded operation of the flash memory and subsequently, during execution of the embedded operation, in response to a received read command, initiating a burst read operation of the flash memory.
1. A method for operating a memory device comprising:
receiving a sector erase command defining a sector erase operation, said sector erase operation comprising six cycles, wherein said sector erase command is issued during a third cycle of said sector erase operation;
during a first time period, issuing said sector erase command at a first data storage bank;
receiving a burst read command defining a burst read operation; and
during a second time period, issuing said burst read command at a second data storage bank, wherein said first time period and said second time period overlap.
2. The method of claim 1 , wherein said burst read operation comprises four cycles, wherein said burst read command is issued during said third cycle of said burst read operation.
3. The method of claim 2 , wherein said sector erase operation further comprises initiating an unlock register command at a first cycle and a second cycle.
4. The method of claim 3 , wherein said sector erase operation further comprises initiating said unlock register command at a fourth cycle and a fifth cycle.
5. The method of claim 4 , wherein said sector erase operation further comprises initiating a sector address command at a sixth cycle.
6. The method of claim 3 , wherein said burst read operation further comprises initiating said unlock register command at said first cycle and said second cycle.
7. The method of claim 4 , wherein said burst read operation further comprises enabling the burst read command at said fourth cycle.
8. A memory device comprising:
a first bank of data storage cells;
a second bank of data storage cells; and
a state machine coupled to said first bank and said second bank, said state machine configured to initiate a sector erase command of an embedded sector erase operation at said first bank during a third clock cycle of said sector erase operation while initiating a burst read command of an embedded burst read operation during said third clock cycle of said burst read operation.
9. The memory device of claim 8 wherein said state machine comprises:
a front end to decode user commands; and
a back end to control embedded operations in response to said user commands.
10. The memory device of claim 9 wherein said front end is configured to decode said burst read command and said back end is configured to control said sector erase command.
11. The memory device of claim 9 wherein said front end is configured to permit execution of a predetermined subset of said user commands, wherein said predetermined subset comprises said burst read command.
12. A method for operating a flash memory, the method comprising:
in response to a received sector erase command, initiating an embedded sector erase operation of a first data storage bank of said flash memory during a third cycle of said sector erase operation, wherein said sector erase operation comprises six cycles, said embedded sector erase operation comprising initiating said sector erase command; and
concurrent to said initiating said sector erase command, in response to a received burst read command, initiating a burst read operation of a second data storage bank of said flash memory during said initiating said sector erase command, said burst read operation comprising initiating said burst read command.
13. The method of claim 12 , wherein said burst read operation comprises four cycles, wherein said initiating said burst read command is issued during said third cycle of said burst read operation.
14. The method of claim 13 , wherein said sector erase operation further comprises initiating an unlock register command at a first cycle and a second cycle.
15. The method of claim 14 , wherein said sector erase operation further comprises initiating said unlock register command at a fourth cycle and a fifth cycle.
16. The method of claim 15 , wherein said sector erase operation further comprises initiating a sector address command at a sixth cycle.
17. The method of claim 14 , wherein said burst read operation further comprises initiating said unlock register command at said first cycle and said second cycle.
18. The method of claim 15 , wherein said burst read operation further comprises enabling the burst read command at said fourth cycle.