Flash memory cell programming method and system
View Patent ↗A flash memory cell programming system and method that facilitate efficient and quick operation of a flash memory cell by providing a biasable well (e.g., substrate) is presented. The biasable well flash memory cell enables increases in electrical field strengths in a manner that eases resistance to charge penetration of a dielectric barrier (e.g., oxide) around a charge trapping region (e.g., a floating gate). The present biasable well system and method also create a self convergence point that increase control during programming operations and reduces the chances of excessive correction for over erased memory cells. The biasing can assist hard programming to store information and/or soft programming to correct the effects of over-erasing. The biasing can also reduce stress on a drain voltage pump, reduce leakage current and reduce programming durations. Some implementations also include a biasable control gate component, biasable source component and biasable drain component.
1. A memory cell comprising:
a control gate component having a capacity to receive a charge;
an oxide region having electrical charge insulation characteristics and electrical charge penetration characteristics, said oxide region coupled to said control gate;
a floating gate having a charge trapping region, said floating gate coupled to said oxide region;
a biasable well component having charge doping characteristics of a first charge nature, wherein said biasable well component is configured to reduce leakage current when a bias voltage is applied to said biasable well, said biasable well coupled to said floating gate component;
a source component having charge doping characteristics opposite of said first charge nature, said source component coupled to said biasable well; and
a drain component having doping charge characteristics opposite of said first charge nature, said drain component coupled to said biasable well.
2. The memory cell of claim 1 wherein said floating gate stores multi-bit information by shifting a threshold voltage in multi-level stages.
3. The memory cell of claim 1 wherein said biasable well component has characteristics that enable an electric field to be increased when a bias voltage is applied to said biasable well.
4. The memory cell of claim 1 wherein said biasable well component has characteristics that aid the movement of charge to and from said floating gate when a bias voltage is applied to said biasable well.
5. The memory cell of claim 1 wherein said source component is configured to reduce the breakdown voltage differential when a bias voltage is applied to said source component.
6. The memory cell of claim 1 wherein said gate component is configured to facilitate the programming of a threshold voltage when a bias voltage is applied to said control gate component.
7. The memory cell of claim 1 wherein said control gate component, said oxide region, said floating gate, said biasable well component, said source component and said drain component have characteristics that reach a self convergence point when a bias is applied to said biasable well.
8. A flash memory method:
biasing a well of a flash memory cell, wherein said biasing causes said flash memory cell to reach a self-convergence point;
storing a charge in a charge trapping region; wherein the amount of charge stored in said charge trapping region is influenced by said biasing of said well; and
removing a charge from a charge trapping region, wherein the amount of charge removed from said charge trapping region is influenced by said biasing of said well.
9. A flash memory method of claim 8 wherein said storing a charge in said charge trapping region facilitates storage of multi-bit information.
10. A flash memory method of claim 8 further comprises:
supplying charges to a floating gate; and
creating a default charge level in said floating gate when said self convergence point is reached.
11. A flash memory method of claim 8 wherein a limit on said well biasing is determined by a junction breakdown voltage.
12. A flash memory method of claim 8 wherein a limit on said well biasing is determined by a back bias voltage.
13. A flash memory method of claim 8 further comprises biasing a source, wherein a limit on said source biasing is determined by a hard carrier generation voltage.
14. A flash memory method of claim 8 further comprising biasing a drain wherein a limit on said drain biasing is determined by a junction breakdown voltage.
15. A flash memory method of claim 8 further comprising biasing a control gate wherein a limit on said gate biasing is determined by a multi-bit storage requirement.
16. A programming method comprising:
increasing an electrical field strength in a well by biasing said well, wherein said biasing is a constant voltage over a write operation; and
altering a charge in a charge trapping region, wherein altering said charge in said charge trapping region forces hot electrons into or out of a charge trapping region and said force is influenced by biasing of said well.
17. A programming method of claim 16 wherein said biasing is a constant voltage over an erase operation.
18. A programming method of claim 17 wherein said altering a charge in said charge trapping region includes applying an erasing voltage differential between a control gate and a drain or source.
19. A programming method of claim 16 wherein said altering a charge in said charge trapping region includes applying a writing voltage differential between a control gate and a drain or source.
20. A programming method of claim 16 wherein said well includes charge doping characteristics of a first charge nature that is opposite to charge doping characteristics of a source component and a drain component.