Patent Assignment
Reel/Frame 019047/0560
Assignment of Assignor's Interest
Recorded: 2007-03-22
Received: 2007-03-22
Pages: 6
Assignor
ADVANCED MICRO DEVICES, INC.
Executed: 2007-01-31
Assignee
SPANSION INC.
915 DEGUIGNE DRIVE, P.O. BOX 3453, MAIL STOP 250, SUNNYVALE, CA, 94088-3453, UNITED STATES
Covered Properties
(35)
Use of High-K Dielectric Material in Modified Ono Structure for Semiconductor Devices
Application:
10/646,080 →
Laser Thermal Annealing Methods for Flash Memory Devices
Application:
10/438,942 →
Implant Damage Removal by Laser Thermal Annealing
Application:
10/378,885 →
Flash Memory Cell Programming Method and System
Application:
10/342,585 →
Bi-Layer Floating Gate for Improved Work Function Between Floating Gate and a High-K Dielectric Layer
Application:
10/274,063 →
Method of Determining the Active Region Width Between Shallow Trench Isolation Structures Using a Gate Current Measurement Technique for Fabricating a Flash Memory Semiconductor Device and Device Thereby Formed
Application:
10/224,737 →
Method of Fabricating a Flash Memory Semiconductor Device by Determining the Active Region Width Between Shallow Trench Isolation Structures Using an Overdrive Current Measurement Technique and a Device Thereby Fabricated
Application:
10/225,052 →
Method of Determining the Active Region Width Between Shallow Trench Isolation Structures Using a C-V Measurement Technique for Fabricating a Flash Memory Semiconductor Device and a Device Thereby Formed
Application:
10/224,028 →
On-Chip Erase Pulse Counter for Efficient Erase Verify Bist (Built-in-Self-Test) Mode
Application:
10/200,330 →
Generation of Margining Voltage on-Chip During Testing Cam Portion of Flash Memory Device
Application:
10/200,539 →
On-Chip Repair of Defective Address of Core Flash Memory Cells
Application:
10/200,544 →
Diagnostic Mode for Testing Functionality of Bist (Built-in-Self-Test) Back-End State Machine
Application:
10/200,526 →
Address Sequencer Within Bist (Built-in-Self-Test) System
Application:
10/200,518 →
Test Structure to Measure Interlayer Dielectric Effects and Breakdown and Detect Metal Defects in Flash Memories
Application:
10/174,734 →
Semiconductor Isolation Material Deposition System and Method
Application:
10/159,078 →
Method for Fabricating Self-Aligned Gate of Flash Memory Cell
Application:
10/150,556 →
Replacing Layers of an Intergate Dielectric Layer with High-K Material for Improved Scalability
Application:
10/145,952 →
Method for Reducing Shallow Trench Isolation Edge Thinning on Tunnel Oxides Using Partial Nitride Strip and Small Bird's Beak Formation for High Performance Flash Memory Devices
Application:
10/126,840 →
Method for Reducing Shallow Trench Isolation Edge Thinning on Thin Gate Oxides to Improve Peripheral Transistor Reliability and Performance for High Performance Flash Memory Devices
Application:
10/126,814 →
Method of Determining Location of Gate Oxide Breakdown of Mosfet by Measuring Currents
Application:
10/113,017 →
Memory Device Having Improved Programmability
Application:
10/103,077 →
Laser Thermal Annealing of Silicon Nitride for Increased Density and Etch Selectivity
Application:
10/096,741 →
Two-Step Source Side Implant for Improving Source Resistance and Short Channel Effect in Deep Sub-0.18MUM Flash Memory Technology
Application:
10/053,256 →
Use of High-K Dielectric Materials in Modified Ono Structure for Semiconductor Devices
Application:
10/036,757 →
Method for Repairing Damage to Charge Trapping Dielectric Layer from Bit Line Implantation
Application:
10/023,349 →
Method of Determining Gate Oxide Thickness of an Operational Mosfet
Application:
10/017,832 →
Non Self-Aligned Shallow Trench Isolation Process with Disposable Space to Define Sub-Lithographic Poly Space
Application:
09/973,131 →
Formation of Sti (Shallow Trench Isolation) Structures Within Core and Periphery Areas of Flash Memory Device
Application:
09/969,573 →
Flash Memory Device with Increase of Efficiency During an Apde (Automatic Program Disturb After Erase) Process
Application:
09/969,572 →
Low Defect Density Process for Deep Sub-0.18UM Flash Memory Technologies
Application:
09/917,182 →
Nor Array with Buried Trench Source Line
Application:
09/917,178 →
N-Gate/N-Substrate or P-Gate/P-Substrate Capacitor to Characterize Polysilicon Gate Depletion Evaluation
Application:
09/917,440 →
Determination of Dielectric Constants of Thin Dielectric Materials in a Mos (Metal Oxide Semiconductor) Stack
Application:
09/904,736 →
High Density Flash Eeprom Array with Source Side Injection
Application:
09/892,685 →
Method of Channel Hot Electron Programming for Short Channel nor Flash Arrays
Application:
09/861,031 →