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US 6,825,083 · Confirmation No. 3418

METHOD FOR REDUCING SHALLOW TRENCH ISOLATION EDGE THINNING ON THIN GATE OXIDES TO IMPROVE PERIPHERAL TRANSISTOR RELIABILITY AND PERFORMANCE FOR HIGH PERFORMANCE FLASH MEMORY DEVICES

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Quick Facts
Patent No.
US 6,825,083
App. No.
10/126,814
Filed
2002-04-19
Granted
2004-11-30
Examiner
LE, THAO X
Art Unit
2814
PTA
-62 days