IP Library Assignment 036036/0490
Patent Assignment
Reel/Frame 036036/0490

Assignment of Assignor's Interest

Recorded: 2015-06-30 Pages: 153
Assignor
SPANSION, LLC
Executed: 2015-06-01
Assignee
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT, SAN JOSE, CALIFORNIA, 95134
Covered Properties (50)
Non-Volatile Memory System Having a Programmably Selectable Boot Code Section Size
Patent: 6,823,435 →
Application: 08/974,971 →
Method for Forming Isolation in Flash Memory Wafer
Patent: 6,808,988 →
Application: 09/019,409 →
Method for Protecting Gate Edges from Charge Gain/Loss in Semiconductor Device
Patent: 6,808,996 →
Application: 09/376,659 →
Method and Apparatus for Improved Performance of Flash Memory Cell Devices
Patent: 6,812,521 →
Application: 09/492,243 →
Dual-Purpose Anti-Reflective Coating and Spacer for Flash Memory and Other Dual Gate Technologies and Method of Forming
Patent: 6,798,002 →
Application: 09/607,675 →
I/O Based Column Redundancy for Virtual Ground with 2-Bit Cell Flash Memory
Patent: 6,813,735 →
Application: 09/676,623 →
Interface Apparatus
Patent: 6,826,192 →
Application: 09/766,001 →
Publication: US 2001/0033575
Clocked Based Method and Devices for Measuring Voltage-Variable Capacitances and Other on-Chip Parameters
Patent: 6,838,869 →
Application: 09/825,027 →
Monos Device Having Buried Metal Silicide Bit Line
Patent: 6,828,199 →
Application: 10/022,798 →
Publication: US 2003/0119314
Innovative Method of Hard Mask Removal
Patent: 6,809,033 →
Application: 10/045,354 →
Partial Page Programming of Multi Level Flash
Patent: 6,836,432 →
Application: 10/074,495 →
Regulator Circuit and Control Method Thereof
Patent: 6,828,764 →
Application: 10/101,976 →
Publication: US 2003/0067283
Liner for Semiconductor Memories and Manufacturing Method Therefor
Patent: 6,803,265 →
Application: 10/109,234 →
Isolation Trench Fill Process
Patent: 6,806,165 →
Application: 10/120,116 →
Method of Detecting and Distinguishing Stack Gate Edge Defects at the Source or Drain Junction
Patent: 6,822,259 →
Application: 10/126,193 →
Method for Reducing Shallow Trench Isolation Edge Thinning on Thin Gate Oxides to Improve Peripheral Transistor Reliability and Performance for High Performance Flash Memory Devices
Patent: 6,825,083 →
Application: 10/126,814 →
System for Control of Pre-Charge Levels in a Memory Device
Patent: 6,816,423 →
Application: 10/136,034 →
Publication: US 2003/0202411
System and Method for Multi-Bit Flash Reads Using Dual Dynamic References
Patent: 6,799,256 →
Application: 10/136,173 →
Publication: US 2003/0208663
Method and System for Scaling Nonvolatile Memory Cells
Patent: 6,806,155 →
Application: 10/150,255 →
Method and System for Determining Flow Rates for Contact Formation
Patent: 6,811,932 →
Application: 10/165,383 →
System for Using a Dynamic Reference in a Double-Bit Cell Memory
Patent: 6,813,189 →
Application: 10/197,116 →
Publication: US 2004/0012993
Reflowable-Doped Hdp Film
Patent: 6,809,402 →
Application: 10/217,403 →
Method of Determining the Active Region Width Between Shallow Trench Isolation Structures Using a C-V Measurement Technique for Fabricating a Flash Memory Semiconductor Device and a Device Thereby Formed
Patent: 6,818,462 →
Application: 10/224,028 →
Floating Gate Memory Device with Homogeneous Oxynitride Tunneling Dielectric
Patent: 6,828,623 →
Application: 10/232,487 →
Methods for Fabricating and Planarizing Dual Poly Scalable Sonos Flash Memory
Patent: 6,797,565 →
Application: 10/244,369 →
Flash Memory Having Improved Core Field Isolation in Select Gate Regions
Patent: 6,815,292 →
Application: 10/260,061 →
Method for Reducing Drain Induced Barrier Lowering in a Memory Device
Patent: 6,833,297 →
Application: 10/265,001 →
System and Method of Forming a Passive Layer by a Cmp Process
Patent: 6,836,398 →
Application: 10/284,769 →
Memory Device Having Resistive Element Coupled to Reference Cell for Improved Reliability
Patent: 6,819,615 →
Application: 10/285,909 →
Mocvd Formation of CU2S
Patent: 6,798,068 →
Application: 10/305,889 →
Publication: US 2004/0102038
Method of Determining Charge Loss Activation Energy of a Memory Array
Patent: 6,813,752 →
Application: 10/306,667 →
Ono Fabrication Process for Reducing Oxygen Vacancy Content in Bottom Oxide Layer in Flash Memory Devices
Patent: 6,803,275 →
Application: 10/308,518 →
Discontinuous Nitride Structure for Non-Volatile Transistors
Patent: 6,828,607 →
Application: 10/315,458 →
Method and System for Testing Tunnel Oxide on a Memory-Related Structure
Patent: 6,808,945 →
Application: 10/339,536 →
Flash Memory Devices with Oxynitride Dielectric as the Charge Storage Media
Patent: 6,797,650 →
Application: 10/342,032 →
Apparatus and Method for a Sense Amplifier Circuit That Samples and Holds a Reference Voltage
Patent: 6,819,612 →
Application: 10/389,149 →
Photosensitive Polymeric Memory Elements
Patent: 6,825,060 →
Application: 10/405,272 →
Fast, Accurate and Low Power Supply Voltage Booster Using a/D Converter
Patent: 6,798,275 →
Application: 10/406,415 →
Publication: US 2004/0196093
Frequency Synthesizer Circuit
Patent: 6,806,782 →
Application: 10/419,206 →
Publication: US 2003/0214360
Method of Controlling Program Threshold Voltage Distribution of a Dual Cell Memory Device
Patent: 6,822,909 →
Application: 10/422,090 →
Nonvolatile Semiconductor Memory Device
Patent: 6,839,279 →
Application: 10/455,310 →
Publication: US 2004/0246784
Structure and Method for Preventing Process-Induced Uv Radiation Damage in a Memory Cell
Patent: 6,833,581 →
Application: 10/460,282 →
Silicon Containing Material for Patterning Polymeric Memory Element
Patent: 6,803,267 →
Application: 10/614,484 →
Partially De-Coupled Core and Periphery Gate Module Process
Patent: 6,835,662 →
Application: 10/619,797 →
Use of High-K Dielectric Material in Modified Ono Structure for Semiconductor Devices
Patent: 6,803,272 →
Application: 10/646,080 →
High Density Floating Gate Flash Memory and Fabrication Processes Therefor
Patent: 6,812,514 →
Application: 10/660,420 →
Neutron Detecting Device
Patent: 6,841,841 →
Application: 10/728,510 →
Structure for Increasing Drive Current in a Memory Array and Related Method
Patent: 6,825,526 →
Application: 10/759,809 →
Method for Erasing a Memory Sector in Virtual Ground Architecture with Reduced Leakage Current
Patent: 6,819,591 →
Application: 10/762,071 →
Memory Device and Methods of Using Negative Gate Stress to Correct Over-Erased Memory Cells
Patent: 6,834,012 →
Application: 10/863,673 →
Related Assignments (19)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Agreement Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
Assignment of Assignor's Interest Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
Termination and Release of Security Interest in Patent Collateral Dec 30, 2014
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 034715/0305 →
Release of Security Interest Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
Security Interest Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
Partial Release of Security Interest in Patents Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
Assignment of Assignor's Interest Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040908/0979 →
Assignment of Assignor's Interest Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
Release of Security Interest Dec 22, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 041178/0061 →
Assignment of Assignor's Interest Mar 29, 2017
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 042108/0880 →
Release of Security Interest Jun 12, 2017
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 042769/0227 →
Release of Security Interest Jun 29, 2017
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 043062/0183 →
Assignment of Assignor's Interest Jul 18, 2017
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 043218/0017 →
Assignment and Assumption of Security Interest in Intellectual Property Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
Corrective Assignment to Correct the 8647899 Previously Recorded on Reel 035240 Frame 0429. Assignor(S) Hereby Confirms the Security Interst. Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
Assignment of Assignor's Interest Jan 26, 2021
From: MONTEREY RESEARCH LLC
To: SPEARHEAD IP LLC
Reel/Frame 055029/0317 →
Assignment of Assignor's Interest Sep 29, 2021
From: SPEARHEAD IP LLC
To: COPPERFIELD LICENSING LLC
Reel/Frame 057638/0064 →
Release of Security Interest Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
Assignment of Assignor's Interest Apr 15, 2022
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES LLC
Reel/Frame 059721/0467 →