Clocked based method and devices for measuring voltage-variable capacitances and other on-chip parameters
View Patent ↗A characterization method for a device under test includes applying a bias voltage to a test circuit. The test circuit includes a first transistor coupled to the device under test, a second transistor coupled to the device under test and to the first transistor. A third transistor is coupled to a dummy device, a fourth transistor is coupled to the dummy device and to the third transistor. The transistors are of a common type. The characterization method further includes applying non-overlapping clocking signals to transistors of the test circuit to produce test signals for application to the device under test and detecting a current in one or more transistors from the device under test. The bias voltage is further varied to characterize the device under test.
1. A test circuit comprising:
a first transistor pair including a first transistor and a second transistor coupled with a device under test; and
a second transistor pair including a third transistor and a fourth transistor coupled with a dummy device, the first transistor and the third transistor having a first common gate connection configured to be driven by a first variable voltage, the first transistor and the third transistor being biased by a first variable bias voltage, the second transistor and the fourth transistor having a second common gate connection configured to be driven by a second variable voltage, the second transistor and the fourth transistor being biased by a second variable bias voltage, wherein the first transistor and the third transistor each comprise a p-channel transistor and the second transistor and the fourth transistor each comprise a p-channel transistor.
2. The test circuit of claim 1 wherein:
the first transistor has a drain coupled to the device under test; and
the second transistor has a source coupled to the device under test.
3. The test circuit of claim 2 wherein:
the third transistor has a drain coupled to the dummy device; and
the fourth transistor has a source coupled to the dummy device.
4. The test circuit of claim 3 where the first transistor, the second transistor, the third transistor and the fourth transistor are formed in an n-well on a p-substrate.
5. The test circuit of claim 4 wherein the first transistor is substantially matched to the third transistor and the second transistor is substantially matched to the fourth transistor.
6. The test circuit of claim 1 further comprising a clock signal generating circuit coupled with the first common gate connection and the second common gate connection and configured to generate the first variable voltage and the second variable voltage.
7. The test circuit of claim 6 wherein the clock signal generating circuit comprises:
an oscillator; and
a frequency division circuit for reducing frequency of signals generated by the oscillator to provide for allowing monitoring frequencies of the first variable voltage and the second variable voltage.
8. The test circuit of claim 7 wherein the frequency division circuit comprises one or more counters.
9. The test circuit or claim 6 wherein the clock signal generating circuit comprises one or more voltage controlled oscillators.
10. The test circuit of claim 9 wherein the clock signal generating circuit further comprises circuitry to control frequency division of the signals generated by the oscillator.
11. The test circuit of claim 1 wherein the device under test and the dummy device comprise multiple electrode capacitances.