METHOD OF FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE BY DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING AN OVERDRIVE CURRENT MEASUREMENT TECHNIQUE AND A DEVICE THEREBY FABRICATED

1. A process for determining the active width of a semiconductor device having a source, drain, and gate comprising the steps of,

measuring the source drain overdrive current of a given device, and

comparing said source drain overdrive current to known source drain overdrive currents correlated to known active widths to determine said active width.

2. The process for determining the active width of a semiconductor device having a source, drain, and gate of claim 1 , wherein said measuring step is performed by biasing said gate of said device in excess of the threshold voltage of said device.

3. The process for determining the active width of a semiconductor device having a source, drain, and gate of claim 2 , wherein said measuring step is performed by biasing said gate of said device by or about one half volt in excess of the threshold voltage of said device.

4. The process for determining the active width of a semiconductor device having a source, drain, and gate of claim 1 , further comprising the steps of;

fabricating a plurality of test semiconductor devices having a source, drain, and gate having drawn active widths which differ by a known distance, and

measuring the source drain overdrive current of each test device, and

comparing the difference in source drain overdrive current of each test device to the known difference in active width of each test device to establish a width value appropriate to a source drain current of zero, and

subtracting said established width value appropriate to a source drain current of zero from said drawn active width to establish a real active width.

5. The process for determining the active width of a semiconductor device having a source, drain, and gate of claim 4 , wherein there are at least three of such test devices.

6. The process for determining the active width of a semiconductor device having a source, drain, and gate of claim 4 , wherein said comparing step is performed by graphing the measured source drain overdrive current on one axis and the corresponding drawn width of each device on another axis to form a set of points, and

extending a line through said points to find the value of the point where the extended line intersects the axis corresponding to zero source drain current, and

taking the value of drawn width at said intersection point, and

subtracting said taken value from said drawn value to find the real value of the active width.

7. The process for determining the active width of a semiconductor device having a source, drain, and gate of claim 6 , wherein at least three of such test devices are used.

8. The process for determining the active width of a semiconductor device having a source, drain, and gate of claim 1 , wherein said device is defined by a plurality of shallow trenches for isolating said device from neighboring devices.

9. The process for determining the active width of a semiconductor device having a source, drain, and gate of claim 8 , wherein said device is a flash device.

10. The process for determining the active width of a semiconductor device having a source, drain, and gate of claim 8 , wherein said the distance between the tops of said shallow trenches is defined as the drawn width of said device.

11. A method of determining an active region width for fabricating a flash memory semiconductor device, comprising the steps of:

(a) forming at least one composite transistor structure, said at least one composite transistor structure comprising:

a semiconductor substrate having a plurality of shallow trench isolation (STI) structures formed therein and a plurality of active regions disposed between successive STI structures;

an insulating layer formed on said substrate; and

a semiconducting layer formed on said insulating layer, at least one transistor element being formed between said successive STI structures at each said active region, each said active region having a predetermined width and an active region width, said predetermined width and said active region width both being distinct for each said at least one composite transistor structure, and each said at least one composite transistor structure having a respective distinct overdrive current value that facilitates determining said active region width; and

(b) determining said respective active region width by:

measuring said respective overdrive current values;

calculating a respective effective composite transistor structure area from the overdrive current value;

calculating said respective active region width from said calculated respective effective composite transistor structure area and a known STI structure length;

subtracting said respective active region width from said respective predetermined width, thereby providing a respective width difference.

12. The method, as recited in claim 11 , wherein said step (a) comprises: forming each said STI structure having opposing upper corner regions; forming said insulating layer comprising a tunnel oxide layer being disposed between said opposing corner regions and having a mid-portion and opposing end portions; and respectively disposing said opposing end portions adjacent said opposing upper corner regions.

13. The method, as recited in claim 11 , wherein said step (a) comprises forming said insulating layer comprising at least one material selected from a group consisting essentially of silicon oxide (SiO) and silicon dioxide (SiO 2 ).

14. The method, as recited in claim 11 , wherein said step (a) comprises forming said semiconducting layer comprising polysilicon (poly-Si).

15. The method, as recited in claim 11 , wherein said step (b) comprises said width difference being a high value and indicating a narrow effective source/drain channel width.

16. The method, as recited in claim 11 , wherein said step (b) comprises said width difference being a low value and indicating a broader effective source/drain channel width.

17. The method, as recited in claim 12 , wherein said step (a) comprises forming said opposing end portions substantially thinner than said mid-portion.