Two-step source side implant for improving source resistance and short channel effect in deep sub-0.18μm flash memory technology
View Patent ↗Methods of forming flash memory EEPROM devices having lightly doped source region near the critical gate region and a heavily doped source region away from the critical gate region. In a first embodiment a first source mask is formed exposing source regions and portions of the gates and implanting n dopant ions, replacing the first source mask with a second source mask that exposes a portion of the source regions and implanting n + dopant ions. In a second embodiment a source mask is formed exposing a portion of the source regions and implanting n + dopant ions.
1. A method of manufacturing a flash memory Electrically-Erasable Programmable Read Only Memory (EEPROM) device having a lightly-doped source region near the critical gate region and a heavily-doped source region away from the critical gate region wherein the lateral diffusion of the source dopants is decreased and having low V ss resistance, and wherein the EEPROM includes a multitude of field effect transistor memory cells each having a source, drain, a floating gate, a control gate and a substrate, the method comprising:
(a) forming multiple gates on a substrate defining drain regions and source regions associated with each of the multiple gates;
(b) forming a first source mask exposing the source regions and portions of the gates;
c) implanting the exposed source regions with n dopant ions;
d) removing the first source mask;
e) forming a second mask exposing a portion of the source and covering a top surface of the gates;
f) implanting the exposed portions of the source region with n + dopant ions; and
g) removing the second source mask.
2. The method of claim 1 further comprising annealing the device.
3. The method of claim 1 wherein step (c) is accomplished by implanting n dopant ions at a low dosage and at low energy.
4. The method of claim 1 wherein step (f) is accomplished by implanting n dopant ions at a high dosage and at high energy.
5. A method of manufacturing a flash memory Electrically-Erasable Programmable Read (Only Memory (EEPROM) device having a lightly-doped source region near the critical gate region and a heavily-doped source region away from the critical gate region wherein the lateral diffusion of the source dopants is decreased and having low V ss resistance, and wherein the EEPROM includes a multitude of field effect transistor memory cells each having a source, drain, a floating gate, a control gate and a substrate, the method comprising:
(a) forming multiple gates on a substrate defining drain regions and source regions associated with each of the multiple gates;
(b) forming a source mask exposing portions of the source region and covering a top surface of the gates;
(c) implanting the exposed portions of the source regions with n + dopant ions; and
(d) removing the source mask.
6. The method of claim 5 further comprising annealing the device.
7. The method of claim 5 wherein step (c) is accomplished by implanting n dopant ions at a high dosage and at high energy.