Structure and method to reduce drain induced barrier lowering
View Patent ↗Embodiments of the present invention include a method for manufacturing a transistor comprising forming a gate conductor above a semiconductor substrate; forming a lightly doped implant region within the substrate, wherein the lightly doped implant region is substantially on the source side of the transistor; and forming a counter doping implant region within the substrate, wherein the counter-doping implant region is substantially on the drain side and wherein the counter-doping reduces the net channel impurity concentration on the drain side.
1. A method for reducing drain induced barrier lowering in a semiconductor having a length between a drain side and a source side comprising:
a) forming a gate stack above a semiconductor substrate, wherein said gate stack masks an area of said drain said and an area of said source side;
b) depositing a source side boron implant in said substrate using only said gate stack to mask said source side; and
c) depositing a drain side counter-doping implant in said substrate using only said gate stack to mask said drain side wherein said drain side counter-doping implant reduces the net channel impurity concentration on said drain side which reduces drain induced barrier lowering.
2. The method as described in claim 1 further comprising annealing said semiconductor, wherein annealing allows said source side boron implant to diffuse to a desired location between said source side and said drain side.
3. The method as described in claim 1 wherein said drain side counter-doping is deposited by an angled implant.
4. The method as described in claim 3 wherein said semiconductor comprises a top surface and wherein said counter-doping is implanted at an angle within 30 degrees of perpendicular to said top surface of said semiconductor.
5. The method as described in claim 1 wherein said counter-doping is arsenic.
6. The method as described in claim 1 wherein said counter-doping is deposited at a dose around 1.0×10 14 particles per square centimeter.
7. The method as described in claim 1 wherein said source side boron implant is deposited at a dose around 1.5×10 14 particles per square centimeter.
8. The method as described in claim 1 wherein said semiconductor is a flash memory cell.
9. The method as described in claim 1 wherein said counter doped drain side results in a graded concentration of net doping across said length between said source and said drain.
10. A method for manufacturing a transistor comprising:
a) forming a gate conductor above a semiconductor substrate, wherein said gate conductor masks an area of said drain said and an area of said source side;
b) forming a lightly doped implant region within said substrate, wherein said lightly doped implant region is substantially on a source side of said transistor using only said gate conductor to mask said source side; and
c) forming a counter doping implant region within said substrate, wherein said counter-doping implant region is substantially on a drain side of said transistor using only said gate conductor to mask said drain side and wherein said counter-doping reduces the net channel impurity concentration on said drain side.
11. The method as described in claim 10 wherein said lightly doped implant region comprises boron.
12. The method as described in claim 10 wherein said counter-doping implant region comprises arsenic.
13. The method as described in claim 10 further comprising annealing said transistor, wherein annealing said transistor promotes diffusion of said counter-doping.
14. The method as described in claim 10 wherein said counter-doping is formed by an angled implant.
15. The method as described in claim 10 wherein said lightly doped implant is formed with a dose of 1.5×10 14 particles per square centimeter.
16. The method as described in claim 10 wherein said counter-doping is formed with a dose of 1.0×10 14 particles per square centimeter.
17. The method as described in claim 10 wherein said transistor is used in a flash memory device.