Non-volatile memory device

1. A memory device, comprising:

a substrate;

an insulating layer formed on the substrate;

a fin structure formed on the insulating layer;

a first oxide layer formed on the fin structure and the substrate;

a nitride layer formed on the first oxide layer, the nitride layer not contacting the insulating layer and acting as a floating gate electrode;

a second oxide layer formed on the nitride layer; and

a control gate formed over the second oxide layer.

2. The memory device of claim 1 , further comprising:

a source region formed on the insulating layer and disposed adjacent a first end of the fin structure; and

a drain region formed on the insulating layer and disposed adjacent a second end of the fin structure.

3. The memory device of claim 1 , wherein the first oxide layer has a thickness ranging from about 110 Å to about 150 Å, the nitride layer has a thickness ranging from about 10 Å to about 180 Å and the second oxide layer has a thickness ranging from about 15 Å to about 200 Å.

4. The memory device of claim 1 , wherein the first oxide layer, the nitride layer and the second oxide layer have a combined thickness ranging from about 40 Å to about 530 Å and functions as a charge storage dielectric.

5. The memory device of claim 1 , wherein the control gate comprises polysilicon and has a thickness ranging about 300 Å to about 4000 Å.

6. The memory device of claim 1 , wherein the insulating layer comprises a buried oxide layer and the fin structure comprises at least one of silicon and germanium.

7. The memory device of claim 6 , wherein the fin structure has a width ranging from about 100 Å to about 3000 Å.

8. A non-volatile memory device, comprising:

a substrate;

an insulating layer formed on the substrate;

a conductive fin formed on the insulating layer;

a first oxide layer formed over the conductive fin;

a nitride layer formed over the first oxide layer, the nitride layer not contacting the insulating layer;

a second oxide layer formed over the nitride layer, wherein the first oxide layer, the nitride layer and the second oxide layer function as a charge storage structure for the non-volatile memory device; and

a gate formed over the second oxide layer, wherein the gate acts as a control gate for the non-volatile memory device.

9. The non-volatile memory device of claim 8 , further comprising:

a source region formed on the insulating layer adjacent a first end of the conductive fin; and

a drain region formed on the insulating layer adjacent a second end of the conductive fin opposite the first end.

10. The non-volatile memory device of claim 8 , wherein the first oxide layer has a thickness ranging from about 15 Å to about 150 Å, the nitride layer has a thickness ranging from about 10 Å to about 180 Å, and the second oxide layer has a thickness ranging from about 15 Å to about 200 Å, wherein the nitride layer acts as a floating gate electrode for the non-volatile memory device.

11. The non-volatile memory device of claim 8 , wherein the gate comprises polysilicon having a thickness ranging from about 300 Å to about 4000 Å in the channel region of the non-volatile memory device.

12. The non-volatile memory device of claim 11 , wherein the insulating layer comprises a buried oxide layer and the conductive fin comprises at least one of silicon and germanium.

13. The non-volatile memory device of claim 8 , wherein the conductive fin functions as a substrate and a bit line and the gate functions as a word line.

14. A non-volatile memory array, comprising:

a substrate;

an insulating layer formed on the substrate;

a plurality of conductive fins formed on the insulating layer, the conductive fins acting as bit lines for the non-volatile memory array;

a plurality of dielectric layers formed over the plurality of fins, the plurality of dielectric layers comprising:

a first oxide layer,

a nitride layer formed over the first oxide layer, the nitride layer acting as a charge storage structure for the non-volatile memory array, wherein the nitride layer does not contact the insulating layer, and

a second oxide layer formed over the nitride layer; and

a plurality of gates formed over the plurality of dielectric layers, the plurality of gates acting as word lines for the non-volatile memory array.

15. The non-volatile memory array of claim 14 , wherein each of the plurality of conductive fins is separated from an adjacent fin by about 500 Å in the lateral direction.