Structure and method for a two-bit memory cell
View Patent ↗According to one exemplary embodiment, a two-bit memory cell situated over a substrate comprises a tunnel oxide layer situated over the substrate. The two-bit memory cell further comprises a first spacer and a second spacer situated over the tunnel oxide layer, where the first spacer is a first data bit storage location in the two-bit memory cell and the second spacer is a second data bit storage location in the two-bit memory cell. The first spacer and the second spacer may be, for example, silicon nitride or polycrystalline silicon. According to this exemplary embodiment, the two-bit memory cell further comprises an oxide layer situated between the first spacer and the second spacer. The two-bit memory cell further comprises a control gate situated over the oxide layer.
1. A two-bit memory cell situated over a substrate, said two bit memory cell comprising:
a tunnel oxide layer situated over said substrate;
a first spacer and a second spacer situated over said tunnel oxide layer, said tunnel oxide layer being situated between said first spacer and said second spacer, said first spacer being a first data bit storage location in said two-bit memory cell and said second spacer being a second data bit storage location in said two-bit memory cell.
2. The two-bit memory cell of claim 1 , further comprising an oxide layer situated between said first spacer and said second spacer.
3. The two-bit memory cell of claim 2 further comprising a control gate situated over said oxide layer.
4. The two-bit memory cell of claim 1 further comprising a source region and a drain region situated in said substrate, said tunnel oxide layer being situated between said source region and said drain region.
5. The two-bit memory cell of claim 1 wherein said first spacer and said second spacer are separated by a distance, said distance being between approximately 5.0 Angstroms and approximately 1000.0 Angstroms.
6. The two-bit memory cell of claim 1 wherein said first spacer and said second spacer comprise silicon nitride.
7. The two-bit memory cell of claim 1 wherein said first spacer and said second spacer comprise polycrystalline silicon.
8. The two-bit memory cell of claim 1 wherein said two-bit memory cell is a two-bit flash memory cell.
9. A two-bit memory cell situated over a substrate, said two-bit memory cell comprising a tunnel oxide layer situated over said substrate, said two-bit memory cell being characterized in that:
a first spacer and a second spacer are situated over said tunnel oxide layer, said tunnel oxide layer being situated between said first spacer and said second spacer, said first spacer being a first data bit storage location in said two-bit memory cell and said second spacer being a second data bit storage location in said two-bit memory cell.
10. The two-bit memory cell of claim 9 further comprising an oxide layer situated between said first spacer and said second spacer.
11. The two-bit memory cell of claim 10 further comprising a control gate situated over said oxide layer.
12. The two-bit memory cell of claim 9 wherein said first spacer and said second spacer are separated by a distance, said distance being between approximately 5.0 Angstroms and approximately 1000.0 Angstroms.
13. The two-bit memory cell of claim 9 wherein said first spacer and said second spacer comprise silicon nitride.
14. The two-bit memory cell of claim 9 wherein said first spacer and said second spacer comprise polycrystalline silicon.
15. The two-bit memory cell of claim 9 wherein said two-bit memory cell is a two-bit flash memory cell.