Semiconductor memory storage device and its redundant method
View Patent ↗A semiconductor memory device includes a memory block having memory cells connected to global bit lines and global word lines are arranged in matrix constitutes a memory block column sharing global bit lines, the memory block column being developed in global word line wiring direction, wherein at least two of memory block columns adjoining each other constitute a to-be-remedied unit, and redundant block(s), which is/are arranged sharing global bit lines with the memory block column(s), which is/are provided in each to-be-remedied unit and number of redundant block(s) is/are smaller than that of memory block column(s) included in the to-be-remedied unit. A minimum number of redundant memory blocks necessary for defectiveness remedy can be provided thereby enhancing the yield with optimization of the manufacturing and circuits. Redundancy remedy efficiency can also be improved while minimizing increased chip die size of the semiconductor memory device.
1. A semiconductor memory device comprising:
bit lines;
word lines intersecting the bit lines;
memory cells connected to the bit lines and the word lines, the memory cells being arranged in a matrix to form a plurality of memory blocks, wherein the plurality of memory blocks are arranged in a bit line wiring direction sharing respective bit lines to form a memory block column arranged in a word line wiring direction, wherein at least two of the memory block columns adjoining each other constitute a to-be-remedied unit; and
redundant memory block(s), which is/are arranged to share bit lines with the memory block column(s), which is/are provided in each to-be-remedied unit for applying redundancy thereto, wherein the number of redundant memory block(s) is/are smaller than the number of memory block column(s) belonging to the to-be-remedied unit.
2. A semiconductor memory device according to claim 1 , wherein the redundant memory block(s) is/are arranged with block(s) divided into redundant memory sub-blocks by the memory block column belonging to the to-be-remedied unit, and
each to-be-remedied memory sub-block has memory capacity equivalent to a memory capacity of the memory block divided by an integer factor (1 is excluded) for factorization of the number of the memory block columns belonging to the to-be-remedied unit.
3. A semiconductor memory device according to claim 2 , wherein the redundant memory sub-blocks are arranged at an end of memory block column(s) in the bit line wiring direction.
4. A semiconductor memory device according to claim 3 , wherein the redundant memory sub-blocks are arranged at either end of the memory block columns in the bit line wiring direction by a unit of the memory capacity of the memory block.
5. A semiconductor memory device according to claim 2 , wherein the redundant memory sub-blocks are arranged in a first well region at least by a unit of the memory capacity of the memory block.
6. A semiconductor memory device according to claim 5 , wherein the first well region is electrically connected with at least one second well region in which at least one memory block is arranged.
7. A semiconductor memory device according to claim 6 , wherein the first well region and the second well region(s) electrically connected thereto are constituted by an identical well region.
8. A semiconductor memory device according to claim 5 , wherein the first well region is formed electrically separate from the second well region(s) in which memory block(s) is/are arranged.
9. A semiconductor memory device according to claim 3 , wherein the redundant memory sub-blocks are arranged in the first well region at least by a unit of the memory capacity of the memory block.
10. A semiconductor memory device according to claim 9 , wherein the first well region is electrically connected with at least one second well region in which at least one memory block is arranged.
11. A semiconductor memory device according to claim 10 , wherein the first well region and the second well region(s) electrically connected thereto are constituted by an identical well region.
12. A semiconductor memory device according to claim 9 , wherein the first well region is formed electrically separate from the second well region(s) in which memory block(s) is/are arranged.
13. A semiconductor memory device according to claim 1 , wherein redundant memory block(s) is/are arranged on region(s) free from memory block(s) existing in the to-be-remedied unit.
14. A semiconductor memory device according to claim 13 , wherein when access information to a predetermined memory block is replaced with information to indicate a specific memory block to be arranged in a specific arrangement position instead of in an essential arrangement position, region(s) free from memory block(s) is/are open region(s) of memory block(s) left in the essential arrangement position based on the access information.