Flash memory device and method of forming the same with improved gate breakdown and endurance
The present invention provides a flash memory device and method for making the same having a floating gate structure with a semiconductor substrate and shallow trench isolation (STI) structure formed in the substrate. A first polysilicon layer is formed over the substrate and the STI structure. The recess formed within the first polysilicon layer is over the STI structure and extends through the first polysilicon layer to the STI structure. An oxide fill is provided within the recess and is etched back. ONO (oxide-nitride-oxide) layer conformally covers the oxide fill and the first polysilicon layer. The second polysilicon layer covers the ONO layer. The oxide fill within the recess provides a minimum spacing between the second polysilicon layer and the corner of the STI regions, thereby avoiding the creation of a weak spot and reducing the risk of gate breakdown, gate leakage, and improving device reliability.
1. A method of forming a flash memory device, comprising the steps of:
forming a first polysilicon layer over a substrate having a shallow trench isolation (STI) region;
etching a recess in the first polysilicon layer over the STI region, the recess extending at least to the STI region;
depositing oxide in the recess;
forming an oxide-nitride-oxide (ONO) layer over the oxide in the recess and over the first polysilicon layer; and
forming a second polysilicon layer on the ONO layer.
2. The method of claim 1 , wherein the step of deposition oxide in the recess includes deposition an oxide film in the recess and on the first polysilicon layer.
3. The method of claim 2 , wherein the step of deposition oxide in the recess further includes blanket oxide etching back of the oxide film until only a portion of the oxide remains in the recess.
4. The method of claim 3 , wherein at least 10% of the recess is filled with the oxide.
5. A method of forming a floating gate transistor, comprising the steps of:
forming a first polysilicon layer over a substrate having a shallow trench isolation (STI) region;
etching a recess in the first polysilicon layer over the STI region, the recess extending at least to the STI region;
forming dielectric spacer material in the bottom of the recess;
forming an oxide-nitride-oxide (ONO) layer on the dielectric spacer material and the first polysilicon layer; and
forming a second polysilicon layer on the ONO layer.
6. The method of claim 5 , wherein the dielectric spacer material comprises an oxide.
7. The method of claim 6 , wherein the step of forming dielectric spacer material includes deposition the oxide in the recess and on the first polysilicon layer.
8. The method of claim 7 , wherein the step of forming dielectric spacer material further includes controllably etching back the deposited oxide until only a portion of the oxide remains in the bottom of the recess.
9. The method of claim 8 , wherein the etching comprises buffered oxide etching.
10. The method of claim 8 , wherein the first polysilicon layer is between about 400 Å to about 1200 Å thick.
11. The method of claim 10 , wherein the dielectric spacer material is between about 50 to about 400 Å thick in the recess.