Granted Patent B2

US 7,102,928 · App. 10/304,762 · Granted Sep 5, 2006

Abstract

Claims (32)

1. A semiconductor memory apparatus having memory cells, comprising:

bit lines connected to said memory cells and divided into at least two fractions;

word lines connected to said memory cells;

reading circuits connectedly provided between the divided bit lines which read data from said memory cells; and

switches which connect the divided bit lines to said reading circuits or disconnecting the divided bit lines from said reading circuits depending on a location of said memory cell of which data are to be read, wherein said bit line is divided at least into a first bit line and a second bit line; and

said reading circuit reads said data from said memory cells connected to said first bit line at a first reading speed, and reads said data from said memory cells connected to said second bit line at a second reading speed different from said first reading speed.

2. The semiconductor memory apparatus as claimed in claim 1 , wherein

said switches, when data stored in said memory cells connected to a first fraction of said bit lines are to be read, disconnects other fractions of said bit lines connected to said reading circuits from said reading circuits.

3. A semiconductor memory apparatus having a NAND-type flash memory including a plurality of serially connected memory cells, comprising:

a bit line divided at least into a first bit line and a second bit line;

said first bit line connected to said memory cells;

said second bit line connected to said memory cells;

a data reading circuit connected between said first bit line and said second bit line which reads data from said memory cells connected to said first bit line or said second bit line; and

a switch, serially connected between the first bit line and the second bit line, which disconnects, when said data are read from said memory cells connected to said first bit line, said second bit line from said data reading circuit.

4. The semiconductor memory apparatus as claimed in claim 3 , wherein said switch disconnects, when said data are read from said memory cells connected to said second bit line, said first bit line from said data reading circuit.

5. The semiconductor memory apparatus as claimed in claim 3 , wherein

said NAND-type flash memory further comprises a select gate transistor connected to said memory cells;

said switch is configured by transistors having the same conductivity type as said select gate transistor.

6. A semiconductor memory apparatus having a plurality of memory cells connected to a bit line and a word line, comprising:

a first memory region including said memory cells that require a first time to access data by activating said bit line and said word line;

a second memory region including said memory cells that requires a second time to access data by activating said bit line and said word line;

a reading circuit provided between said firt memory region and said second memory region, that, in whichever said first memory region or said second memory region accessed memory cells are included, reads said data from the accessed memory cells; and

a switch, connectedly provided between said reading circuit and said second memory region, which disconnects, when said reading circuit reads said data from said first memory region, said second memory region from said reading circuit, wherein

said bit line is divided at least into a first bit line and a second bit line; and

said reading circuit leads said data from said memory cells connected to said first bit line at first reading speed, and reads said data from said memory cells connected to said second bit line at a second reading speed different from said first reading speed.

7. A semiconductor memory apparatus having a memory cell array configured by a plurality of memory cells, comprising:

a bit line connected to the plurality of memory cells and divided at least into two fractions;

a word line connected to the plurality of memory cells;

a reading circuit connected to an end of said bit line and disposed at a side of said memory cell array, which reads data from said memory cells; and

a switch which connects the divided bit line to said reading circuit or disconnects the divided bit line from said reading circuit depending on a location of said memory cell of which data are to be read, wherein

said bit line is divided at least into a first bit line and a second bit line; and

said reading circuit reads said data from said memory cells connected to said first bit line at a first reading speed, and reads said data from said memory cells connected to said second bit line at a second reading speed different from said first reading speed.

Assignments (10)