Horizontal MOS transistor
View Patent ↗This invention provides a horizontal MOS transistor capable of improving current drivability and reducing ON resistance by optimizing the gate wiring structure and the disposition structure of source/drain layers. First gate wirings are disposed in the X direction at a pitch Y 1 in the Y direction and second gate wirings 12 are disposed in the Y direction with two pieces as a pair such that they meander at a pitch X 1 in the X direction. The meandering of the second gate wiring 12 is formed so as to sandwich the bent portions 14 substantially in the center of the pitch Y 1 . A bottle-like shape diffusion layer region in which the wide-width region and narrow-width region are combined is sectioned by adjacent first and second wirings. A contact 16 for connecting the diffusion layer region to the wiring layer 18 is disposed in the wide-width region and wiring layers 18 are disposed such that two rows run in parallel in the X direction. A diffusion layer region is a different electrode region from diffusion layer regions adjacent on four sides thereby forming a MOS transistor. Consequently, a horizontal MOS transistor excellent in current drivability for each unit region and having a slight ON resistance is constructed.
1. A horizontal MOS transistor comprising:
first gate wirings arranged taking a first predetermined pitch in a second direction crossing a first direction, the first gate wirings being wired in the first direction; and
second gate wirings being paired and arranged taking a second predetermined pitch pair by pair at wiring layer same as wiring layer of the first gate wirings, the second gate wirings being wired in the second direction,
wherein the second gate wiring has a bend section at between adjoining two of the first gate wirings and meander by the first predetermined pitch.
2. A horizontal MOS transistor according to claim 1 , wherein adjoining two of the second gate wirings meander in a mirror symmetry manner and the bend section is at substantially center of the second direction between adjoining two of the first gate wirings.
3. A horizontal MOS transistor according to claim 2 , wherein a diffusion layer region surrounded by adjoining two of the first gate wirings and adjoining two of the second gate wirings is arranged such that,
in the first direction, a pair of a narrow-width region and a wide-width region is arranged sandwiching the bend sections on the second direction and positioning of the pair of the narrow-width region and the wide-width region is reversed alternatingly, and
in the second direction, either the narrow-width region or the wide-width region is arranged facing each other across a second gate wiring.
4. A horizontal MOS transistor according to claim 3 , wherein the wide-width region has a contact which connects the diffusion layer region and wiring layer.
5. A horizontal MOS transistor according to claim 4 , wherein the contact is arranged in two rows between adjoining two of the first gate wirings along the first direction, and the wiring layer is wired along the first gate wiring with encompassing the contact.
6. A horizontal MOS transistor according to claim 1 , wherein the first gate wiring is wired linearly.
7. A horizontal MOS transistor according to claim 1 , wherein the first gate wiring and the second gate wiring cross in orthogonal angle.
8. A horizontal MOS transistor according to claim 5 , wherein two rows of the wiring layers wired along the first gate wiring are connected different terminals respectively in the horizontal MOS transistor.
9. A horizontal MOS transistor according to claim 8 , wherein the diffusion layer region connected to two rows of the wiring layers correspond to drain layer and source layer for the horizontal MOS transistor.
10. A horizontal MOS transistor according to claim 5 , wherein two rows of the wiring layers wired along the first gate wiring are connected different terminals respectively in the horizontal MOS transistor, and the narrow-width region has two kinds of upper contacts which connect each of the wiring layers and two sets of upper wiring layers common to each of the wiring layers.
11. A horizontal MOS transistor according to claim 10 , wherein the two kinds of upper contacts connect every other wiring layer of the two rows of wiring layers and different two sets of upper wiring layers.
12. A horizontal MOS transistor according to claim 10 , wherein the two sets of upper wiring layers are wired crossing the wiring layers.
13. A horizontal MOS transistor according to claim 12 , wherein the two sets of upper wiring layers are wired extending in the second direction.
14. A horizontal MOS transistor according to claim 10 , wherein the two sets of upper wiring layers are arranged in planner state crossing the wiring layers.
15. A horizontal MOS transistor according to claim 10 , wherein the horizontal MOS transistor constitutes a power transistor.
16. A horizontal MOS transistor according to claim 1 , wherein the horizontal MOS transistor is built in a semiconductor integrated circuit device for power control.
17. A horizontal MOS transistor according to claim 10 , wherein the power control includes control of switching power supply.
18. A horizontal MOS transistor according to claim 1 , wherein the horizontal MOS transistor is used as an output stage transistor.
19. A semiconductor device for power control having a MOS transistor, the MOS transistor comprising:
first gate wirings arranged taking a first predetermined pitch in a second direction crossing a first direction, the first gate wirings being wired in the first direction; and
second gate wirings being paired and arranged taking a second predetermined pitch pair by pair at wiring layer same as wiring layer of the first gate wirings, the second gate wirings being wired in the second direction,
wherein the second gate wiring has a bend section at between adjoining two of the first gate wirings and meander by the first predetermined pitch.
20. A semiconductor device for power supply having a MOS transistor, the MOS transistor comprising:
first gate wirings arranged taking a first predetermined pitch in a second direction crossing a first direction, the first gate wirings being wired in the first direction; and
second gate wirings being paired and arranged taking a second predetermined pitch pair by pair at wiring layer same as wiring layer of the first gate wirings, the second gate wirings being wired in the second direction,
wherein the second gate wiring has a bend section at between adjoining two of the first gate wirings and meander by the first predetermined pitch.