Quad bit using hot-hole erase for CBD control
View Patent ↗The present invention pertains to a technique for erasing bits in a dual bit memory in a manner that maintains complementary bit disturb control of bit-pairs of memory cells wherein each bit of the dual bit memory cell can be programmed to multiple levels. One exemplary method comprises providing a word of memory cells after an initial erasure and programming of the bits of the word to one or more of the higher program levels. A disturb level is determined for each of the bit-pairs of the word. A combined disturb level is then computed that is representative of the individual disturb levels. A pattern of drain voltages is then applied to the word for a number of program passes until a target pattern is stored in the word of memory cells based on the combined disturb level and the unprogrammed bit of the bit-pairs is erased to a single program level. In this manner the present invention compensates for the disturbance level that exists between the complementary bit-pairs of the word, improves the Vt distribution at the program level of the erased state and thereby improves the accuracy of subsequent higher level programming operations and mitigates false or erroneous reads of the states of such program levels.
1. A method of erasing to maintain complimentary bit disturb control of a group of complementary bit-pairs of memory cells, each bit having multiple programming levels, the method comprising:
comparing the program levels of a programmed bit and a complimentary unprogrammed bit within the bit-pairs of the group of memory cells to determine a disturb level for each bit-pair of the group;
determining a combined disturb level representative of the individual disturb levels determined for the bit-pairs of the group;
setting a drain voltage and a number of program passes for a target pattern to be stored in the memory cell based on the combined disturb level determined for the group; and
erasing the unprogrammed bit of the bit-pairs to one of the program levels using the drain voltage and the number of program passes of the target pattern based on the combined disturb level to compensate for the disturbance level that exists between the complementary bit-pairs of the group of memory cells.
2. The method of claim 1 , further comprising:
providing the group of memory cells after an initial erasure of the group.
3. The method of claim 2 , further comprising:
providing the group of memory cells after a subsequent programming of a portion of the bits of the group to one or more higher program levels.
4. The method of claim 1 , wherein the group of complementary bit-pairs of memory cells comprises a word of memory cells.
5. The method of claim 4 , wherein the group of memory cells is selected from a single word line.
6. The method of claim 4 , wherein the word comprises one or more complementary bit-pairs of memory cells.
7. The method of claim 6 , wherein setting a drain voltage and a number of program passes for a target pattern to be stored in the memory cell based on the combined disturb level determined for the group comprises:
determining if the combined disturb level is greater than a predetermined value; and
applying a float condition, a first drain voltage, and a first inhibit voltage comprising a first pattern and an associated first number of program passes of a first target pattern to the group of memory cells if the combined disturb level is greater than the predetermined value; otherwise
applying a float condition, a second drain voltage, and a second inhibit voltage comprising a second pattern and an associated second number of program passes of a second target pattern to the group of memory cells if the combined disturb level is greater than the predetermined value
storing into the group of memory cells the selected pattern in the associated number of program passes at the applied float condition, drain voltage, and inhibit voltage selected based on the combined disturb level.
8. The method of claim 7 , wherein the first drain voltage is about 6 volts and the first inhibit voltage is about 3 volts.
9. The method of claim 7 , wherein the second drain voltage is about 4 volts and the second inhibit voltage is about 0 volts.
10. The method of claim 7 , wherein the first number of program passes comprises three passes of the first pattern.
11. The method of claim 7 , wherein the second number of program passes comprises two passes of the second pattern.
12. The method of claim 1 , wherein comparing the program levels of a programmed bit and a complimentary unprogrammed bit within the bit-pairs of the group of memory cells to determine a disturb level for each bit-pair of the group comprises:
reading the associated program level of the programmed bit and the associated program level of each bit-pair; and
subtracting the associated program level of the programmed bit from the associated program level of the unprogrammed bit to provide a disturb level for each bit-pair.
13. The method of claim 1 , wherein comparing the program levels of a programmed bit and a complimentary unprogrammed bit within the bit-pairs of the group of memory cells to determine a disturb level for each bit-pair of the group comprises:
determining the Vt levels of the programmed and the unprogrammed bits of each bit-pair; and
subtracting the Vt level of the programmed bit from the Vt level of the unprogrammed bit to provide a disturb level for each bit-pair.
14. The method of claim 1 , wherein determining the combined disturb level representative of the individual disturb levels determined for the bit-pairs of the group comprises computing one of an average, mean, sum, sigma, and another math function representative of the individual disturb levels.
15. The method of claim 1 , wherein erasing the unprogrammed bit of the bit-pairs to one of the program levels comprises erasing the unprogrammed bit of the bit-pairs to a lowest level of the program levels.
16. The method of claim 1 , wherein the combined disturb level is selected from one of the programming levels.
17. The method of claim 1 , wherein the multiple programming levels comprises four programming levels.
18. A method of erasing to maintain complimentary bit disturb control of complementary bit-pairs of a word grouping of memory cells, each bit having multiple programming levels, the method comprising:
providing the word of memory cells after an initial erasure and programming of a portion of the bits of the word to one or more higher program levels;
comparing the program levels of a programmed bit and a complimentary unprogrammed bit within the bit-pairs of the word grouping of core memory cells to determine a disturb level for each bit-pair of the word grouping;
determining a combined disturb level representative of the individual disturb levels determined for the bit-pairs of the word;
setting a drain voltage and a number of program passes for a target pattern to be stored in the memory cell based on the combined disturb level determined for the word; and
erasing the unprogrammed bit of the bit-pairs to one of the program levels using the drain voltage and the number of program passes of the target pattern based on the combined disturb level to compensate for the disturbance level that exists between the complementary bit-pairs of the word.
19. The method of claim 18 , wherein the word of core memory cells comprises memory cells selected from a single word line.
20. The method of claim 19 , wherein the word comprises one or more complementary bit-pairs of memory cells.
21. A method of erasing to maintain complimentary bit disturb control of a complementary bit-pair of a core memory cell having multiple programming levels, the method comprising:
providing the complementary bit-pair having a bit programmed to a higher one of the multiple program levels;
determining the level of an unprogrammed bit of the bit-pair based upon a comparison with the possible program levels of the bit;
determining a disturb compensation level for the unprogrammed bit based upon a comparison of the difference between the program level of the programmed bit and the level determined for the unprogrammed bit;
setting a drain voltage and a number of program passes for a target pattern to be stored in the memory cell corresponding to the disturb compensation level determined; and
erasing the unprogrammed bit of the bit-pair to one of the program levels using the drain voltage and the number of program passes of the target pattern based on the disturb compensation comparison.