Granted Patent B1

US 7,074,677 · App. 10/307,189 · Granted Jul 11, 2006

Abstract

Claims (12)

1. A method of manufacturing an integrated circuit comprising:

depositing a first dielectric layer on a semiconductor substrate;

depositing with an oxygen anneal a low hydrogen charge-trapping layer over the first dielectric layer for preventing charge loss;

a second dielectric layer over the charge-trapping layer;

forming first and second bitlines in the semiconductor substrate;

forming a wordline over the second dielectric layer; and

completing the integrated circuit.

2. The method of manufacturing an integrated circuit as claimed in claim 1 wherein depositing the low hydrogen charge-trapping layer uses precursors that combine to produce a low hydrogen deposition.

3. The method of manufacturing an integrated circuit as claimed in claim 1 wherein depositing the low hydrogen charge-trapping layer deposits a nitride.

4. The method of manufacturing an integrated circuit as claimed in claim 1 wherein depositing the low hydrogen charge-trapping layer uses plasma enhanced chemical vapor deposition at a temperature above 500° C. without using ammonia.

5. The method of manufacturing an integrated circuit as claimed in claim 1 wherein depositing the low hydrogen charge-trapping layer uses a plasma enhanced chemical vapor deposition at temperature above 500° C. with an anneal at a temperature above 600° C.

6. The method of manufacturing an integrated circuit as claimed in claim 1 wherein depositing the low hydrogen charge-trapping layer deposits a nitride and depositing the first and second dielectric layers deposits oxides.

Assignments (14)