Alignment marks with salicided spacers between bitlines for alignment signal improvement
View Patent ↗The present invention pertains to utilizing a salicide in establishing alignment marks in semiconductor fabrication. A metal layer is formed over exposed portions of a silicon substrate as well as oxide areas formed over bitlines buried within the substrate. The metal layer is treated to react with the exposed portions of the silicon substrate to form salicided areas. The metal layer does not, however, react with the oxide areas. As such, salicided areas are formed adjacent to the oxide areas to provide an enhanced optical contrast when light is shined there-upon. In this manner, the alignment marks can be more readily “seen”. The enhanced optical contrast thus allows the marks to continue to be seen as scaling occurs.
1. A method of forming and using an alignment mark on a semiconductor substrate comprising:
forming buried bitlines within the semiconductor substrate, the buried bitlines having respective widths;
forming respective oxides over the buried bitlines, the oxides having respective widths that are greater than or equal to the widths of the buried bitlines such that the bitlines are completely covered by the respective oxides;
forming a metal layer over the substrate;
treating the metal layer to form salicides on the substrate adjacent to the oxide areas but not over the buried bitlines; and
removing excess unreacted metal and exposing the salicided and oxide areas.
2. The method of claim 1 , further comprising:
shining a light at the salicided and oxide areas; and
observing a contrast between light reflected from the salicided and oxide areas.
3. The method of claim 2 , further comprising:
utilizing the contrast to determine a condition of alignment.
4. The method of claim 3 , further comprising:
selectively adjusting an orientation of the substrate based upon the determined condition of alignment.
5. The method of claim 1 , wherein the metal layer comprises at least one of titanium (Ti), cobalt (Co) and nickel (Ni).
6. The method of claim 1 , wherein the respective oxides are formed by forming a layer of oxide material over the buried bitlines and exposed portions of the silicon substrate, and removing some of the oxide material such that oxide remains over the buried bitlines, but not over portions of the substrate adjacent thereto.
7. The method of claim 6 , wherein some of the oxide is removed via etching.
8. The method of claim 6 , wherein the layer of oxide material is formed by dopant enhancement oxidation.
9. The method of claim 1 , wherein forming buried bitlines comprises:
implanting a dopant through one or more apertures defined within a patterned resist mask and through one or more oxide-nitride-oxide (ONO) layers formed over the substrate and underlying the patterned resist mask; and
removing the one or more ONO layers and patterned resist mask overlying the buried bitlines.
10. The method of claim 9 , wherein the one or more ONO layers define a charge-trapping dielectric layer.
11. The method of claim 9 , wherein the charge-trapping dielectric layer includes a first insulating layer of silicon dioxide (SiO 2 ), a charge-trapping layer of silicon nitride (Si x N y ), and a second insulating layer of silicon dioxide (SiO 2 ).
12. A method of forming and using an alignment mark on a semiconductor substrate comprising:
forming salicides on the substrate adjacent to oxide areas formed on the substrate, the oxide areas being formed over bitlines implanted into the substrate and being formed to respective widths that are greater than or equal to respective widths of the bitlines such that the bitlines are completely covered by the respective oxides and the salicides are not formed over the bitlines.
13. The method of claim 12 , further comprising:
shining a light at the substrate, the light being reflected differently from the salicided and oxide areas to yield contrast data.
14. The method of claim 13 , further comprising:
utilizing contrast data to develop one or more control signals that facilitate selective maneuvering of the substrate to establish appropriate alignment.
15. An alignment mark formed on a semiconductor substrate, comprising:
an oxide area formed over a buried bitline formed within the substrate; and
a salicide formed on the substrate adjacent to the oxide area, where the oxide area is formed to a width that is greater than or equal to the width of the bitline such that the bitline is completely covered by the oxide and the salicide is not formed over the bitline.
16. The alignment mark of claim 15 , wherein the salicide and oxide area provide an optical contrast when light is directed at and reflected from the same.
17. The alignment mark of claim 16 , wherein the contrast provided by the salicide and oxide areas can be utilized to develop one or more control signals that facilitate selective maneuvering of the substrate to establish appropriate alignment.
18. A semiconductor substrate having an alignment mark formed thereon comprising:
an oxide area formed over a buried bitline formed within the substrate; and
a salicide formed on the substrate adjacent to the oxide area, where the oxide area is formed to a width that is greater than or equal to the width of the bitline such that the bitline is completely covered by the oxide and the salicide is not formed over the bitline.
19. The semiconductor substrate of claim 18 , wherein the salicide and oxide area provide an optical contrast when light is directed at and reflected from the same.
20. The semiconductor substrate of claim 19 , wherein the contrast provided by the salicide and oxide areas can be utilized to develop one or more control signals that facilitate selective maneuvering of the substrate to establish appropriate alignment.