Method for programming dual bit memory devices to reduce complementary bit disturbance
View Patent ↗The present invention provides a method for programming a selected bit in a memory cell of a non-volatile dual bit flash memory device. The method includes applying a positive voltage to a bit line associated with the selected bit and applying another positive voltage to a word line associated with the selected bit. Next, a positive voltage is applied to a second bit line associated with a complementary bit that shares the memory cell with the selected bit. A positive voltage is also applied to a third bit line that is adjacent to the second bit line and removed from the bit line associated with the selected bit by the second bit line. Applying a negative voltage to the word line then erases the complementary bit, but not its adjacent non-selected bit. The programming cycle is repeated until a desired threshold voltage is obtained.
1. A method for programming a selected bit in a memory cell of a non-volatile dual bit flash memory device comprising:
pulsing said selected bit, and wherein said pulsing comprises:
applying a first positive voltage to a first bit line associated with said selected bit; and
applying a second positive voltage to a word line associated with said selected bit;
performing a counter erase on a complementary bit, wherein said performing a counter erase further comprises:
applying a third positive voltage to a second bit line associated with a complementary bit that shares said memory cell with said selected bit;
applying a fourth positive voltage to a third bit line, adjacent to said second bit line and separated from said first bit line by said second bit line, said fourth positive voltage for preventing erasure of a non-selected bit in an adjacent memory cell, and said non-selected bit sharing said second bit line with said complementary bit; and
erasing said complementary bit by applying a negative voltage to said word line;
verifying that said selected bit is sufficiently programmed, wherein said verifying further comprises:
applying fifth positive voltage to said second bit line;
applying a sixth positive voltage to said word line; and
repeating said programming until the read current of said verifying reaches a value less than a reference level value.
2. The method as recited in claim 1 , wherein said memory cell resides in an array of memory cells, each said memory cell comprising a normal bit and a complementary bit.
3. The method as recited in claim 2 , wherein said selected bit comprises said normal bit.
4. The method as recited in claim 3 wherein said counter-erase operation reduces complementary bit disturbance.
5. In a dual bit memory device comprising at least one non-volatile memory cell, a method for programming said non-volatile memory cell, comprising:
applying a first positive voltage to a first bit line associated with a selected bit in a first phase of a programming cycle;
applying a second positive voltage to a word line associated with said selected bit in said first phase of said programming cycle;
applying a third positive voltage to a second bit line associated with a complementary bit that shares said memory cell with said selected bit in a second phase of said programming cycle;
applying, in said second phase of said programming cycle, a fourth positive voltage to a third bit line that is adjacent to said second bit line and separated from said first bit line by said second bit line, said fourth positive voltage for preventing erasure of a non-selected bit in an adjacent memory cell, said non-selected bit sharing said second bit line with said complementary bit;
erasing said complementary bit by applying a negative voltage to said word line in said second phase of said programming cycle;
applying fifth positive voltage to said second bit line in a third phase of said programming cycle;
applying a sixth positive voltage to said word line in said third phase; and
repeating said programming cycle said sixth positive voltage reaches a threshold voltage.
6. The method as recited in claim 5 wherein said first phase of said programming cycle comprises programming said selected bit.
7. The method as recited in claim 5 wherein said second phase of said programming cycle comprises a counter-erase operation.
8. The method as recited in claim 7 wherein said counter-erase operation is for reducing complementary bit disturbance.
9. The method as recited in claim 5 wherein said third phase of said programming cycle comprises verifying that said sixth positive voltage equals a threshold voltage defined as a programmed level.
10. The method as recited in claim 5 , wherein said fourth positive voltage has a value that comprises one-half the value of said third positive voltage.
11. The method as recited in claim 5 , wherein said memory cell resides in an array of memory cells, each comprising a normal bit and a complementary bit.
12. The method as recited in claim 11 , wherein said selected bit comprises said normal bit.
13. A method for programming a first bit in a memory cell of a dual bit flash memory device, said memory cell comprising said first bit and a second bit, comprising:
applying a first positive voltage to a first bit line associated with said first bit in a first phase of a programming cycle;
applying a second positive voltage to a word line associated with said first bit in said first phase of said programming cycle;
applying a third positive voltage to a second bit line associated with said second bit that shares said memory cell with said first bit in a second phase of said programming cycle;
applying, in said second phase of said programming cycle, a fourth positive voltage to a third bit line that is adjacent to said second bit line and separated from said first bit line by said second bit line, said fourth positive voltage for preventing erasure of a non-selected bit in an adjacent memory cell, said non-selected bit sharing said second bit line with said second bit; and
erasing said second bit by applying a negative voltage to said word line in said second phase of said programming cycle.
14. The method as recited in claim 13 further comprising:
applying fifth positive voltage to said second bit line in a third phase of said programming cycle;
applying a sixth positive voltage to said word line in said third phase; and
repeating said programming cycle until a read current of said first bit is less than a reference current.
15. The method as recited in claim 13 wherein said second phase of said programming cycle comprises a counter-erase operation.
16. The method as recited in claim 15 wherein said counter-erase operation reduces complementary bit disturbance.
17. The method as recited in claim 12 wherein said third phase of said programming cycle comprises verifying that said sixth positive voltage equals a threshold voltage defined as a programmed level.
18. The method as recited in claim 13 , wherein said fourth positive voltage has a value that comprises one-half the value of said third positive voltage.