Non-volatile semiconductor memory, semiconductor device and charge pump circuit
View Patent ↗A non-volatile semiconductor memory includes a first pump starting to operate at a first timing and producing a first voltage, a second pump starting to operate at a second timing following the first timing and driving a given node at a second voltage, the given node being connected to a non-volatile semiconductor memory cell, and a booster boosting the given node using the first voltage at the second timing.
1. A non-volatile semiconductor memory comprising:
a first pump starting to operate at a first timing and producing a first voltage;
a second pump starting to operate at a second timing following the first timing and driving a given node at a second voltage, the given node being connected to a non-volatile semiconductor memory cell; and
a booster boosting the given node using the first voltage at the second timing.
2. The non-volatile semiconductor memory as claimed in claim 1 , wherein a period from the first timing to the second timing is provided for program verification and another period starting from the second timing is provided for programming.
3. The non-volatile semiconductor memory as claimed in claim 1 , wherein the booster comprises:
a capacitor;
a first circuit that allows the first voltage to be applied to the given node during a period from the first timing to the second timing; and
a second circuit applying a voltage based on the first voltage to the given node during only a predetermined period starting from the second timing.
4. The non-volatile semiconductor memory as claimed in claim 3 , wherein the capacitor is also used for generating a read voltage applied to the gate of the non-volatile semiconductor memory at the time of reading data.
5. The non-volatile semiconductor memory as claimed in claim 1 , wherein the second pump comprises a plurality of boost stages, and nodes between adjacent boost stages among the plurality of boost stages are precharged by the first voltage during a period from the first timing to the second timing.
6. The non-volatile semiconductor memory as claimed in claim 5 , wherein the second pump circuit comprises transistors which apply the first voltage to the nodes in response to a signal indicating the period from the first timing to the second timing.
7. The non-volatile semiconductor memory as claimed in claim 1 , wherein the first voltage is applied to a bit line to which the non-volatile semiconductor memory is connected at the time of programming.
8. A charge pump circuit comprising:
a first pump starting to operate at a first timing and producing a first voltage; and
a second pump starting to operate at a second timing following the first timing and driving a given node at a second voltage,
the second pump including a plurality of boost stages, wherein nodes between adjacent boost stages among the plurality of boost stages are precharged by the first voltage during a period from the first timing to the second timing.
9. The charge pump circuit as claimed in claim 8 , wherein the second pump circuit comprises transistors which apply the first voltage to the nodes in response to a signal indicating the period from the first timing to the second timing.
10. A semiconductor device comprising:
a non-volatile semiconductor memory cell;
a first pump starting to operate at a first timing and producing a first voltage; and
a second pump starting to operate at a second timing following the first timing and driving a given node at a second voltage, the given node being connected to the non-volatile semiconductor memory cell,
the second pump including a plurality of boost stages, wherein nodes between adjacent boost stages among the plurality of boost stages are precharged by the first voltage during a period from the first timing to the second timing.
11. The semiconductor device as claimed in claim 10 , wherein the second charge pump includes a transistor that applies the first voltage to the given node in response to a signal indicating a period from the first timing to the second timing.
12. The semiconductor device as claimed in claim 10 , wherein the first voltage is applied to a bit line to which the non-volatile semiconductor memory is connected at the time of programming.
13. A method comprising the steps of:
starting up an operation of a first pump at a first timing to produce a first voltage;
starting up an operation of a second pump at a second timing following the first timing to drive a given node at a second voltage, the given node being connected to a non-volatile semiconductor memory cell; and
boosting the given node using the first voltage at the second timing.
14. A method comprising the steps of:
starting up an operation of a first pump at a first timing to produce a first voltage;
starting up an operation of a second pump at a second timing following the first timing to drive a given node at a second voltage, the given node being connected to a non-volatile semiconductor memory cell; and
precharging nodes between adjacent boost stages among a plurality of boost stages of the second pump by the first voltage during a period from the first timing to the second timing.