Granted Patent B2

US 7,068,555 · App. 11/061,307 · Granted Jun 27, 2006

Abstract

Claims (36)

1. A semiconductor memory device comprising:

bit lines;

word lines wired orthogonally on the bit lines;

memory cells connected to the bit lines and the word lines, the memory cells being arranged in a matrix to form a memory block, a plurality of which are arranged in a bit line wiring direction sharing respective bit lines to form memory block columns arranged in word line wiring direction, at least one memory block column including a redundancy memory block arranged sharing bit lines with a memory block for remedying a defective memory block;

a block redundancy judge section for selecting a redundancy memory block from at least redundancy memory block(s) by outputting a redundancy block select signal in case a memory block including inputted address information is a defective memory block;

a block column designate section for designating a memory block column inclusive of a selected redundancy memory block by outputting a column designate signal depending on the redundancy block select signal; and

a column redundancy control section for conducting column redundant control by memory block column including a redundant memory block,

wherein column redundant control of a selected redundant memory block is conducted by the column redundant control section depending on the column designate signal.

2. A semiconductor memory device according to claim 1 , wherein the block column designate section designates a memory block column in accordance with inputted address information in case the redundant block select signal is not inputted, and designates a memory block column in accordance with the redundant block select signal irrespective of inputted address information in case the redundant block select signal is inputted.

3. A semiconductor memory device according to claim 1 , wherein the column redundancy control section includes a to-be-remedied information memory section in which to-be-remedied column address information relating a memory block or/and a redundancy memory block included in a memory block column is stored.

4. A semiconductor memory device according to claim 1 , wherein at least two of memory block columns adjoining each other constitute a to-be-remedied unit and, in each of the to-be-remedied unit, number of redundant memory block(s) is smaller than that of memory block column(s) belonging to the to-be-remedied unit.

5. A semiconductor memory device according to claim 4 , wherein

redundant memory block(s) is/are arranged with block(s) divided into redundant memory sub-blocks by the memory block column belonging to the to-be-remedied unit, and

each to-be-remedied memory sub-block has memory capacity equivalent to memory capacity of the memory block divided by a factor (1 is excluded) for factorization of the number of memory block columns belonging to the to-be-remedied unit.

6. A semiconductor memory device according to claim 4 , wherein redundant memory block(s) is/are arranged on region(s) free from memory block(s) existing in the to-be-remedied unit.

7. A semiconductor memory device according to claim 1 , wherein memory cells are non-volatile memory cells, and the memory block and the redundant memory block are a unit of batch erase.

8. A semiconductor memory device comprising:

a plurality of bit lines each of which is connected to a plurality of memory cells, at least one of bit lines is connected to at least one redundant memory cell(s); and

a bias voltage supply section for supplying high bias voltage to memory cells or/and redundant memory cells through bit line depending on length of the bit line, wherein, in the case where redundancy processing is not conducted, the bias voltage supply section supplies a bias voltage value based on address information which indicates a connection point of bit line and memory cell and in the case where redundancy processing is conducted, defruiting of the address information is executed in accordance with a redundancy select signal and the bias voltage supply section supplies a bias voltage value based on length of bit line reaching redundant memory cell.

9. A semiconductor memory device according to claim 8 , wherein, in the case where the length of bit lines from the bias voltage supply section to a plurality of redundant memory cells differs, the bias voltage supply section supplies a bias voltage value in accordance with a redundancy select signal which differs by respective redundant memory cells.

10. A semiconductor memory device according to claim 8 , wherein the bias voltage supply section includes:

a voltage set section for setting voltage division ratio of bias voltage in accordance with the address information or/and the redundancy select signal; and

a voltage adjust section for adjusting a target bias voltage value by adjusting divided voltage set by the voltage set section to reference voltage.

11. A semiconductor memory device according to claim 10 wherein the voltage set section sets voltage division ratio depending on capacity ratio of capacitance devices connected in series.

12. A semiconductor memory device according to claim 8 wherein memory cells are unified as memory block by predetermined number of bit lines and predetermined length of bit line,

redundant memory cells are included in redundant memory block for block redundancy,

the address information is for identifying memory block in bit line length direction, and

the redundancy select signal is for identifying redundant memory block to be selected for block redundancy.

13. A semiconductor memory device according to claim 8 , wherein memory cells and redundant memory cells are non-volatile memory cells, and bias voltage supplied by the bias voltage supply section is voltage to be applied when memory information is written or erased.

14. A redundancy control method in a semiconductor memory device comprising bit lines; word lines wired orthogonally on the bit lines; and memory cells connected to the bit lines and the word lines, the memory cells being arranged in matrix to form a memory block, a plurality of memory blocks being arranged in bit line wiring direction sharing respective bit lines to form memory block column arranged in word line wiring direction, the redundancy control method comprising the steps of:

a block redundancy judge step for judging whether or not to apply block redundancy to redundant memory block(s) which is/are arranged sharing bit lines with at least one memory block column(s) with respect to inputted address information;

a column redundancy judge step for judging whether or not apply block redundancy by memory block column; and

a column redundancy control step where in case the block redundancy judge step judges not to apply block redundancy, column redundancy information of memory block column corresponding to the address information is supplied to the column redundancy judge step, and in the case where the block redundancy judge step judges to apply block redundancy, column redundancy information of a memory block column in which a redundancy memory block is arranged is supplied to the column redundancy judge step.

15. A redundancy control method for a semiconductor memory device comprising a plurality of bit lines each of which is connected to a plurality of memory cells, at least one of bit lines is connected to at least one redundant memory cell(s), for supplying bias voltage to memory cells or/and redundant memory cells through bit line, the redundancy control method comprising the steps of:

a first voltage adjust step for adjusting bias voltage to high level in accordance with address information corresponding to length of bit line reaching memory cell, namely, a connection point of bit line and memory cell, in case redundancy processing is not conducted; and

a second voltage adjust step for adjusting bias voltage to high level in accordance with a redundancy select signal corresponding to length of bit line reaching memory cell instead of the address information in case redundancy processing is conducted.

Assignments (10)