Granted Patent B1

US 7,071,538 · App. 11/008,263 · Granted Jul 4, 2006

Abstract

Claims (35)

1. A structure for use in a semiconductor device, comprising:

a first oxide layer;

a charge storage layer formed upon the first oxide layer;

a steam oxide layer thermally grown upon the charge storage layer; and

an alumina oxide layer formed upon the steam oxide layer.

2. The structure of claim 1 , wherein the charge storage layer comprises a nitride.

3. The structure of claim 2 , wherein the nitride comprises silicon nitride.

4. The structure of claim 2 , wherein the first oxide layer is formed upon a substrate comprising silicon.

5. The structure of claim 4 , further comprising:

a gate electrode formed adjacent the steam oxide layer, wherein the gate electrode comprises silicon.

6. The structure of claim 4 , further comprising:

source, drain and channel regions formed within the substrate.

7. The structure of claim 5 , wherein the semiconductor device comprises a silicon-oxide-nitride-oxide-silicon (SONOS) memory device.

8. The structure of claim 1 , wherein the alumina oxide layer has a thickness ranging from about 70 Å to about 140 Å.

9. The structure of claim 1 , wherein the steam oxide layer has a thickness ranging from about 30 Å to about 60 Å.

10. A method of forming a charge retention structure for a semiconductor device, comprising:

forming a first oxide layer upon a substrate;

forming a charge storage layer upon the first oxide layer;

thermally growing an oxide layer upon the charge storage layer in a water vapor or steam environment; and

forming an alumina oxide layer upon the thermally grown oxide layer.

11. The method of claim 10 , wherein the charge storage layer comprises a nitride.

12. The method of claim 11 , wherein the nitride comprises silicon nitride.

13. The method of claim 10 , wherein the substrate comprises silicon.

14. The method of claim 10 , further comprising:

forming a control gate electrode on the thermally grown oxide layer, wherein the control gate electrode comprises silicon.

15. The method of claim 10 , wherein the oxide layer is thermally grown to a thickness ranging from about 30 Å to about 60 Å.

16. A memory device, comprising:

a substrate comprising source, drain and channel regions;

a bottom oxide layer formed upon the substrate;

a charge storage layer formed upon the bottom oxide layer;

a thermally grown oxide layer formed upon the charge storage layer;

an alumina oxide layer formed upon the thermally grown oxide layer; and

a gate electrode formed upon the alumina oxide layer.

17. The memory device of claim 16 , wherein the charge storage layer comprises a nitride layer.

18. The memory device of claim 16 , wherein the thermally grown oxide layer is formed in a steam environment.

Assignments (7)