Bare die carrier
View Patent ↗A bare semiconductor circuit die carrier is provided for use in the test of semiconductor circuits, the carrier, comprising: a substrate defining an opening and an outer perimeter; a multiplicity of I/O pads disposed about the perimeter; an interconnect circuit which includes a composite of a multiplicity of individual electrical conductors which are formed in a polymer dielectric; wherein the interconnect circuit overlays a top surface of the substrate and extends across the opening so as to form a flexible membrane that spans the opening; a multiplicity of die contact pads connected to the conductors are disposed about the flexible membrane with particles deposited on the die contact pads; a fence upstanding from the membrane and sized to receive a test die; a top cap that rests upon the die when the die is received within the fence; a bottom cap that rests against a bottom surface of the substrate; and a fastener for securing the top cap to the bottom cap with the die disposed therebetween.
1. A temporary carrier assembly comprising:
a substrate/interconnect circuit having
device contact pads adapted to make contact with a semiconductor device,
input/output pads, and
electrical conductors that connect the device contact pads with the input/output pads;
a top cap that is not connected electrically to the substrate/interconnect circuit; and
at least one fastening mechanism for selectively holding the substrate/interconnect circuit and top cap together to form the temporary carrier assembly with the semiconductor device between them and, when they are being held together, for forcing the semiconductor device against the device contact pads.
2. The assembly of claim 1 wherein the substrate/interconnect circuit comprises a substrate.
3. The assembly of claim 2 wherein the device contact pads, the input/output pads, and the electrical conductors are coupled to the substrate.
4. The assembly of claim 1 wherein the substrate/interconnect circuit includes a compliant region.
5. The assembly of claim 4 wherein the support comprises a substrate and the compliant region comprises a thinned region of the substrate.
6. The assembly of claim 4 wherein the compliant region comprises a membrane.
7. The assembly of claim 6 wherein:
the substrate/interconnect circuit comprises a substrate having an opening, and the membrane extends across the opening.
8. The assembly of claim 2 wherein the substrate/interconnect circuit further comprises a bottom cap.
9. The assembly of claim 8 wherein the bottom cap is rigid.
10. The assembly of claim 8 wherein the substrate/interconnect circuit further comprises a support mounted on the bottom cap to urge a plurality of device contact bumps into a common plane.
11. The assembly of claim 1 wherein the input/output pads do not substantially project from the substrate/interconnect circuit.
12. The assembly of claim 1 wherein the substrate/interconnect circuit comprises a membrane.
13. The assembly of claim 12 wherein the membrane comprises a polymer dielectric.
14. The assembly of claim 12 wherein the substrate/interconnect circuit comprises a substrate and a thin film interconnect extending over a top surface of the substrate, the membrane being a portion of the thin film interconnect.
15. The assembly of claim 14 wherein the carrier assembly further comprises a support configured to contact a bottom surface of the membrane to urge a plurality of device contact bumps into a common plane.
16. The assembly of claim 15 in which the support comprises a semiconductor element.
17. The assembly of claim 15 in which the support comprises a flexible member.
18. The assembly of claim 17 in which the support comprises an elastomer.
19. The assembly of claim 15 in which the support comprises a spring and a shim.
20. The assembly of claim 15 in which the support comprises an elastomer and a spring.
21. The assembly of claim 15 in which the insert comprises a spherical ball bearing.
22. The assembly of claim 1 wherein the coefficient of thermal expansion of the substrate/interconnect circuit substantially matches the coefficient of thermal expansion of the semiconductor device.
23. The assembly of claim 1 wherein the substrate/interconnect circuit further comprises a fence configured to receive the semiconductor device.
24. The assembly of claim 1 wherein the device contact pads have rough surfaces.
25. The assembly of claim 24 wherein the rough surfaces are formed of oxide penetrating particles.
26. The assembly of claim 1 wherein the top cap is spring biased.
27. The assembly of claim 26 wherein the lid further comprises posts coupled to the support; a cap configured to be selectively coupled to the posts; and a resilient mechanism that exerts a force between the cap and the semiconductor device when the cap is coupled to the posts.
28. The assembly of claim 1 wherein the input/output pads are adapted to couple to a printed wiring board.